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A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar

Authors:

Chengmo Yang,

Zeyu ChenAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 195 - 200

https://doi.org/10.1145/3299874.3317972

Published: 13 May 2019 Publication History

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Abstract

Processing-In-Memory (PIM), which implements logic operations within memory cells, opens up a new direction on organizing data and computation. Leveraging resistive or magnetic characteristics of nonvolatile memory (NVM) devices, platforms such as PLiM and ReVAMP have been proposed. This paper presents a PIM implementation of SHA-3, a state-of-the-art secure hash algorithm using a Voltage-Gated Spin Hall-Effect (SHE) Driven magnetic tunnel junction (MTJ) based crossbar, which is able to achieve a complete set of Boolean operations. The work includes the design of the crossbar circuit, the instruction set, and both unpipelined and pipelined implementations of SHA-3. Experimental results show that the proposed SHE MTJ-based implementation is able to achieve 2.16X higher throughput than a state-of-the-art Resistive RAM based SHA-3 implementation. Further throughput improvement can be achieved with multiple message hash (MMH) pipelining.

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Cited By

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Oved BLeitersdorf ORonen RKvatinsky S(2022)HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST54814.2022.9837685(1-4)Online publication date: 8-Jun-2022
https://doi.org/10.1109/MOCAST54814.2022.9837685

Index Terms

A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging architectures
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs
      1. Hardware accelerators
    2. Semiconductor memory
      1. Non-volatile memory

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Information

Published In

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 May 2019

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National Science Foundation

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GLSVLSI '19

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SIGDA

GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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June 30 - July 2, 2025

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Cited By

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Oved BLeitersdorf ORonen RKvatinsky S(2022)HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST54814.2022.9837685(1-4)Online publication date: 8-Jun-2022
https://doi.org/10.1109/MOCAST54814.2022.9837685

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Redesign the Memory Allocator for Non-Volatile Main Memory

Towards memory-efficient processing-in-memory architecture for convolutional neural networks

Large-Scale BSP Graph Processing in Distributed Non-Volatile Memory