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Improving AES Core Performance via an Advanced ASBUS Protocol

Published: 11 December 2017 Publication History

Abstract

Security is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding efficiency of the Advanced Encryption Standard (AES) encrypted circuits. As a case study, the direct memory access (DMA) combined with AES engine and memory controller are implemented as our design-under-test (DUT) using field-programmable gate arrays (FPGA). The results show that our presented ASBUS structure outperforms the AXI-based design for cipher tests. As an example, the 32-bit ASBUS design costs less in terms of hardware resources and achieves higher throughput (1.30 ×) than the 32-bit AXI implementation, and the dynamic energy consumed by the ASBUS cipher test is reduced to 71.27% compared with the AXI test.

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Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 14, Issue 1
January 2018
289 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/3143783
  • Editor:
  • Yuan Xie
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 December 2017
Accepted: 01 June 2017
Received: 01 December 2016
Published in JETC Volume 14, Issue 1

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Author Tags

  1. Advanced encryption standard (AES)
  2. advanced exensible interface (AXI)
  3. bus protocol
  4. filed-programmable gate array (FPGA)
  5. system-on-chips (SoC)

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  • (2021)An IoT-Edge-Server System with BLE Mesh Network, LBPH, and Deep Metric LearningAdvances in Artificial Intelligence and Applied Cognitive Computing10.1007/978-3-030-70296-0_55(757-773)Online publication date: 15-Oct-2021
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  • (2018)Exploring Slice-Energy Saving on an Video Processing FPGA Platform with Approximate ComputingProceedings of the 2nd International Conference on Algorithms, Computing and Systems10.1145/3242840.3242852(138-143)Online publication date: 27-Jul-2018
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  • (2018)Embedded System Confidentiality Protection by Cryptographic Engine Implemented with Composite Field ArithmeticMATEC Web of Conferences10.1051/matecconf/201821002047210(02047)Online publication date: 5-Oct-2018

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