Decoupling loads for nano-instruction set computers
Pages 406 - 417
Abstract
We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers can generate better static instruction schedules by hoisting a decoupled load's data access above may-alias stores and branches. We find that decoupled loads improve performance with geometric mean speedups of 8.4%.
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Published: 18 June 2016
Published in SIGARCH Volume 44, Issue 3
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