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Complexity-effective superscalar processors

Authors:

Subbarao Palacharla,

Norman P. Jouppi,

J. E. SmithAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 25, Issue 2

Pages 206 - 218

https://doi.org/10.1145/384286.264201

Published: 01 May 1997 Publication History

Abstract

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of 0.8µm, 0.35µm, and 0.18µm. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future.A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore, because only instructions at queue heads need to be awakened and selected, issue logic is simplified and the clock cycle is faster --- consequently overall performance is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.

References

[1]

E S. Ahuja, D. W. Clark, and A. Rogers. The Performance Impact of Incomplete Bypassing in Processor Pipelines. in Proceedings of the 28th Annual International Symposium on Microarchitecture, November 1995.

Digital Library

[2]

C. Asato, R. Montoye, J. Gmuender, E. W. Simmons, A. Ike, and J. Zasio. A 14-port 3.Sns ll6-word 64b Read-Renaming Register F'de. In 1995 IEEE International Sold-State Circuits Conference Digest of Technical Papers, pages 104-105, February 1995.

[3]

Mark T. Bohr. Interconnect Sealing - The Real Limiter to High Performance ULSI. in 1995 International Electron Devices Meeting Technical Digest, pages 241-244, 1995.

[4]

Doug Burger, Todd M. Austin, and Steve Bennett. Evaluating Future Microprocessors: The Simplesealar Tool Set. Technical Report CS- TR-96-1308 (Available from http'.//www.cs.wisc.edtt/trs.html), University of Wisconsin-Madison, July 1996.

[5]

M. Butler and Y. N. Patt. An investigation of the Performance of Various Dynamic Scheduling Techniques. In Proceedings of the 25th An. nual International S~ymposium on Microarchitecture, pages I-9, December 1992.

Digital Library

[6]

Keith I. Farkas, Norman P. Jouppi, and Paul Chow. Reglster File Design Considerations in Dynamically Scheduled Processors. In Proceedings of the Second IEEE Symposium on High.Performance Conl. purer Architecture, February 1996.

Digital Library

[7]

Linley Gwennap. Speed Kills? Not for RISe Processors, Micropro. cessor Report, 7(3):3, March 1993.

[8]

Linley Gwennap. HAL Reveals Multichip SPARC Processor, Micro. processor Report, 9(3), March 1995.

[9]

Linley Gwermap. Intel's P6 Uses Deeoupled Supersealar Design, Microprocessor Report, 9(2), February 1995.

[10]

Jim Keller. The 21264: A Supersealar Alpha Processor with Out-of- Order Execution, October 1996. 9th Annual Microprocessor Forum, San Jose, California.

[11]

Gregory A. Kemp and Manoj Franklin, PEWs: A Decentralized Dynamic Scheduler for ILP Processing. In Proceedings of the lnterna. tional Conference on Parallel Processing, volume I, pages 239-246, 1996.

[12]

Ashok Kumar. The HP-PA8000 RISC CPU: A High Performance Outof-Order Processor. In Proceedings of the Hot Chips VIII, pages 9-20, August 1996.

[13]

Scott MeFarling. Combining Branch Predictors. DEC WRL Technical Note TN-36, DEC Western Research Laboratory, 1993.

[14]

Meta-Software inc. HSpice User's Manual, June 1987,

[15]

Subbarao Palaeharla, Norman P. Jouppl, and James E. Smith, Quantifying the Complexity of Supersealar Processors. Technical Report CS- TR-96-1328 (Available from http'J/www.es.wise.edu/trs,html), University of Wisconsin-Madison, November 1996.

[16]

S. Peter Song, Marvin Denman, and Joe Chang. The PowerPC 604 RISC Microprocessor. In IEEE Micro, pages 8--17, October 1995,

Digital Library

[17]

N. Vasseghi et al. 200 MHz Supersealar RISC Processor Circuit Design Issues. in 1996 IEEE International Sold-State Circuits Conference Digest of Technical Papers, pages 356--357, February 1995,

[18]

Tomohisa Wada, Suresh Rajan, and Stevea A, Przybylski, An Analytical Access Tune Model for On-Chip Cache Memories. IEEE Journal of Solid.State Circuits, 27(8):1147-1156, August 1992,

[19]

Neil H.E. Weste and Kamran Eshraghian. Principles of CMOS VLSI Design. Addison Wesley, second edition, 1993,

Digital Library

[20]

Nell C. Wilhelm. Why Wire Delays Will No Longer Scale for VLSI Chips. Technical Report SMI.,I TR-95-44, Sun Mierosystems Laboratories, August 1995.

[21]

Steven J. E. Wilton and Norman P. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches. Technical Report 93/5, DEC Western Research Laboratory, July 1994.

[22]

K.C. Yeager. MIPS RI0000 Supersealar Microprocessor, In IEEE Micro, April 1996.

Digital Library

Cited By

Hu YChen JZhu KXing QLiu WShen JGao G(2022)Specially-Designed Out-of-Order Processor Architecture for MicrocontrollersElectronics10.3390/electronics1119298911:19(2989)Online publication date: 21-Sep-2022
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Complexity-effective superscalar processors

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 25, Issue 2

Special Issue: Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97)

May 1997

349 pages

ISSN:0163-5964

DOI:10.1145/384286

Editors:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan

Issue’s Table of Contents

ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture
June 1997
350 pages
ISBN:0897919017
DOI:10.1145/264107
Chairmen:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan

Copyright © 1997 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1997

Published in SIGARCH Volume 25, Issue 2

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Cited By

Hu YChen JZhu KXing QLiu WShen JGao G(2022)Specially-Designed Out-of-Order Processor Architecture for MicrocontrollersElectronics10.3390/electronics1119298911:19(2989)Online publication date: 21-Sep-2022
https://doi.org/10.3390/electronics11192989
MATSUDA YSHIOYA RANDO H(2022)Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag ComparisonIEICE Transactions on Information and Systems10.1587/transinf.2021EDP7174E105.D:2(320-332)Online publication date: 1-Feb-2022
https://doi.org/10.1587/transinf.2021EDP7174
Wu ZChai LZhao NDeng BLiu YWen QWang JHe S(2022)Make Your Own SpritesACM Transactions on Graphics10.1145/3550454.355548241:6(1-16)Online publication date: 30-Nov-2022
https://dl.acm.org/doi/10.1145/3550454.3555482
Zhang LWong TLiu Y(2022)Sprite-from-SpriteACM Transactions on Graphics10.1145/3550454.355543941:6(1-12)Online publication date: 30-Nov-2022
https://dl.acm.org/doi/10.1145/3550454.3555439
Diavastos ACarlson T(2022)Efficient Instruction Scheduling Using Real-time Load Delay TrackingACM Transactions on Computer Systems10.1145/354868140:1-4(1-21)Online publication date: 24-Nov-2022
https://dl.acm.org/doi/10.1145/3548681
Mohammadi MHan SAtoofian EBaniasadi AAamodt TDally W(2020)Energy Efficient On-Demand Dynamic Branch Prediction ModelsIEEE Transactions on Computers10.1109/TC.2019.295671069:3(453-465)Online publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1109/TC.2019.2956710
Alipour MKaxiras SBlack-Schaffer DKumar R(2020)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00042(424-434)Online publication date: Feb-2020
https://doi.org/10.1109/HPCA47549.2020.00042
Li YWu MYe XLi WXue RWang DZhang HFan D(2020)An Efficient Scheduling Algorithm for Dataflow Architecture Using Loop-PipeliningInformation Sciences10.1016/j.ins.2020.09.029Online publication date: Oct-2020
https://doi.org/10.1016/j.ins.2020.09.029
Alipour MKumar RKaxiras SBlack-Schaffer D(2019)FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715034(716-721)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715034
Balsini APannocchi LCucinotta T(2019)Modeling and simulation of power consumption and execution times for real-time tasks on embedded heterogeneous architecturesACM SIGBED Review10.1145/3373400.337340816:3(51-56)Online publication date: 25-Nov-2019
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