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Investigating optimal local memory performance

Published: 01 October 1998 Publication History

Abstract

Recent work has demonstrated that, cache space is often poorly utilized. However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN algorithm does yield an upper bound, but exploits only temporal locality. In this article, we present an optimal replacement algorithm for local memory that exploits temporal locality and spatial locality simultaneously. This algorithm is an extension of Belady's algorithm. We prove the optimality of this new algorithm with respect to minimizing misses, and we show experimentally that the algorithm produces nearly minimum memory traffic on the SPEC95 benchmarks. Like Belady's algorithm, our algorithm requires the entire program trace. It selects replacement victims and the number of words it fetches at once based on future accesses. Many different spatial locality strategies can be implemented with this algorithm. With an optimal strategy, the algorithm yields an upper bound that enables us to evaluate alternative implementations to today's caches. We further demonstrate the utility of this algorithm as an analysis tool by evaluating several intermediate strategies between cache and optimal to highlight the limitations of the cache line paradigm using the SPEC95 benchmarks.

References

[1]
Santosh G. Abraham and Rabin A. Sugumar. Efficient simulation of caches under optima} replacement with applications to miss characterization. In Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems, 1993.
[2]
L. A. Belady. A Study of Replacement Algorithms for a Virtual-Storage Computer. IBM Systems Journal, 5(2):78- 101, 1966.
[3]
D. Burger, A. K~gi, and J. R. Goodman. Memory bandwidth limitations of future microprocessors. In Proceedings of the 23rd A CM International Symposium on Computer Architecture, Philadelphia, May 1996.
[4]
Douglas C. Burger, Alan Kagi, and James R. Goodman. The Declining Effectiveness of Dynamic Caching for General- Purpose Microprocessors. Technical Report 1261, University of Wisconsin, Madison, April 1996.
[5]
Pei Cao, Edward Felten, Anna Karlin, and Kai Li. A study of integrated prefetching and caching strategies. In Proceedings of A CM International Conference on Measurement and Modeling of Computer Systems, pages 188-196, Ottawa, Canada, May 1995.
[6]
K. K. Chan, C. C. Hay, J. R. Keller, G. P. Kurpanek, F. X. Schumacher, and J. Sheng. Design of the hp pa-7200 cpu. Hewlett-Packard Journal, February 1996.
[7]
Digital Equipment Corporation. Atom, user manual. Technical report, Digital Equipment Corporation, Maynard, Massachusetts, June 1995.
[8]
John W. C. Fu, Janak H. Patel, and B. L. Janssens. Stride Directed Prefetching in Scalar Processors. In Proceedings of the 26th IEEE International Symposium on Microarchitecture, 1992.
[9]
Elana D. Cranston and Alexander V. Veidenbaum. An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems. In International Conference on Parallel Processing, volume II, pages 83-90, August 1991.
[10]
John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach, 2nd Edition. Morgan Kaufmann Publishers Inc., 1996.
[11]
L. P. Horwitz, R. M. Karp, R. E. Miller, and S. Winograd. Index register allocation. ACM Journal, 13(1):43-61, January 1966.
[12]
Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small, Fully-Associative Cache and Prefetch Buffers. In Proceedings of the 17th A CM International Symposium on Computer Architecture, pages 364- 373, May 1990.
[13]
R.L. Mattson, J. Gecsei, D.R. Slutz, and I.L. Traiger. Evaluation techniques for storage hierarchies. IBM Systems journal, 9(2):78-117, 1970.
[14]
S. McFarling. Cache Replacement with Dynamic Exclusion. In Internal Symposium on Computer Architecture, 1992.
[15]
Kathryn S. McKinley and Olivier Temam. A quantitative analysis of loop nest locality. In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, October 1996.
[16]
Jesus Sanchez, Antonio Gonzalez, and Mateo Valero. Software Management of Selective and Dual Data Caches . in IEEE TCCA Newsletter, March 1997.
[17]
Andr{~ Seznec. A Case for Two-Way Skewed-Associative Caches. In Proceedings of the 20th International Symposium on Computer Architecture, pages 169-178, San Diego, May 1993.
[18]
Andr~ Seznec. Decoupled sectored caches' Conciliating low tag implementation cost and low miss ratio. In Proceedings of the 21th International Symposium on Computer Architecture, pages 384--393, 1994.
[19]
Olivier Temam. Investigating optimal local memory performance. Technical Report 97/25, PRISM, Versailles University, December 1997.

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Published In

cover image ACM SIGOPS Operating Systems Review
ACM SIGOPS Operating Systems Review  Volume 32, Issue 5
Dec. 1998
309 pages
ISSN:0163-5980
DOI:10.1145/384265
Issue’s Table of Contents
  • cover image ACM Conferences
    ASPLOS VIII: Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
    October 1998
    326 pages
    ISBN:1581131070
    DOI:10.1145/291069
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 1998
Published in SIGOPS Volume 32, Issue 5

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