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Slipstream processors: improving both performance and fault tolerance

Authors:

Karthik Sundaramoorthy,

Eric RotenburgAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 28, Issue 5

Pages 257 - 268

https://doi.org/10.1145/378995.379247

Published: 12 November 2000 Publication History

Abstract

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor simultaneous multithreaded processor, with two key advantages:1) Improved single-program performance. The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2) Fault tolerance. The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.

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Cited By

Psychou GRodopoulos DSabry MGemmeke TAtienza DNoll TCatthoor F(2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
https://dl.acm.org/doi/10.1145/3092699
Koser EBerthold KKumar Pujari RStechele W(2016)A Chip-level Redundant Threading (CRT) scheme for shared-memory protection2016 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCSim.2016.7568324(116-124)Online publication date: Jul-2016
https://doi.org/10.1109/HPCSim.2016.7568324
Mehta S(2023)Speculative Register Reclamation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071122(1182-1194)Online publication date: Feb-2023
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Index Terms

Slipstream processors: improving both performance and fault tolerance

Recommendations

Slipstream processors: improving both performance and fault tolerance
ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...
Slipstream processors: improving both performance and fault tolerance

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...
Slipstream processors: improving both performance and fault tolerance

Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the ...

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 28, Issue 5

Special Issue: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems (ASPLOS '00)

Dec. 2000

269 pages

ISSN:0163-5964

DOI:10.1145/378995

Editor:
Doug DeGroot
Dallas, TX

Issue’s Table of Contents

ASPLOS IX: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
November 2000
271 pages
ISBN:1581133170
DOI:10.1145/378993
Chairmen:
Larry Rudolph
MIT, Cambridge, MA
,
Anoop Gupta
Microsoft

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 November 2000

Published in SIGARCH Volume 28, Issue 5

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https://dl.acm.org/doi/10.1145/3092699
Koser EBerthold KKumar Pujari RStechele W(2016)A Chip-level Redundant Threading (CRT) scheme for shared-memory protection2016 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCSim.2016.7568324(116-124)Online publication date: Jul-2016
https://doi.org/10.1109/HPCSim.2016.7568324
Mehta S(2023)Speculative Register Reclamation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071122(1182-1194)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071122
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