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A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)

Published: 28 January 2000 Publication History
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References

[1]
N. Weste and K. Eshraghian, Principles of CMOS VLSI Design - A Systems Perspective Addition-Wesley Publishers, 1985.
[2]
T. Kim, W. Jao, and S. Tjiang, "Circuit Optimization using Carry-Save-Adder Cells ", IEEE TCAD October 1998.
[3]
J. Um, T. Kim, C. L. Liu, "Optimal Allocation of Carry-Save- Adders in Arithmetic Optimization ", Proc. ICCAD, 1999.
[4]
Synopsys Inc., Design Ware Components Databook, 1996.
[5]
LSI Logic Inc., G10-p Cell-Based ASIC Products Databook, 1996.

Cited By

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  • (2006)Optimizing high speed arithmetic circuits using three-term extractionProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131838(1294-1299)Online publication date: 6-Mar-2006
  • (2006)Optimizing High Speed Arithmetic Circuits Using Three-Term ExtractionProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.244103(1-6)Online publication date: 2006
  • (2001)Signal representation guided synthesis using carry-save adders for synchronous data-path circuitsProceedings of the 38th annual Design Automation Conference10.1145/378239.378560(456-461)Online publication date: 22-Jun-2001

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cover image ACM Conferences
ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference
January 2000
691 pages
ISBN:0780359747
DOI:10.1145/368434
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2000

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Cited By

View all
  • (2006)Optimizing high speed arithmetic circuits using three-term extractionProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131838(1294-1299)Online publication date: 6-Mar-2006
  • (2006)Optimizing High Speed Arithmetic Circuits Using Three-Term ExtractionProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.244103(1-6)Online publication date: 2006
  • (2001)Signal representation guided synthesis using carry-save adders for synchronous data-path circuitsProceedings of the 38th annual Design Automation Conference10.1145/378239.378560(456-461)Online publication date: 22-Jun-2001

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