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The ZS-1 central processor

Published: 05 October 1987 Publication History

Abstract

The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. Descriptions of the instruction set, pipeline structure, and virtual memory implementation demonstrate the methods used to satisfy the objectives. High performance is achieved through a combination of static (compile-time) instruction scheduling and dynamic (run-time) scheduling. Both types of scheduling are illustrated with examples.

References

[1]
{FISH83} J. A. Fisher, "Very Long Instruction Word Architectures and the ELI-512", 10th Annual International Symposium on Computer Architecture, Stockholm, Sweden, pp. 140--150, June 1983.
[2]
{HENN83} J. L. Hennessy, et al., "Design of a High Performance VLSI Processor," 3rd Caltech Conference on VLSI, pp. 33--54, Mar. 1983.
[3]
{SMIT86} J. E. Smith, S. Weiss, and N. Y. Pang, "A Simulation Study of Decoupled Architecture Computers," IEEE Transactions on Computers, pp. 692--702, Aug. 1986.
[4]
{THOR70} J. E. Thornton, Design of a Computer - The Control Data 6600, Scott, Foresman and Co., Glenview, IL, 1970.
[5]
{WOR81} J. Worlton, "The Philosophy Behind the Machines," Computer World Nov. 9. 1981.

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cover image ACM Conferences
ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems
October 1987
205 pages
ISBN:0818608056
DOI:10.1145/36206
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Published: 05 October 1987

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  • (2011)OUTRIDERProceedings of the 38th annual international symposium on Computer architecture10.1145/2000064.2000079(117-128)Online publication date: 4-Jun-2011
  • (2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
  • (2009)Advances in Software PipeliningThe Compiler Design Handbook10.1201/9781420043839.ch20(20-1-20-73)Online publication date: 7-Dec-2009
  • (2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009
  • (2006)Performance of the decoupled ACRI-1 architecture: The perfect clubHigh-Performance Computing and Networking10.1007/BFb0046669(472-480)Online publication date: 2-Feb-2006
  • (2005)A limitation study into access decouplingEuro-Par'97 Parallel Processing10.1007/BFb0002859(1102-1111)Online publication date: 26-Sep-2005
  • (2005)Increasing memory bandwidth for vector computationsProgramming Languages and System Architectures10.1007/3-540-57840-4_26(87-104)Online publication date: 31-May-2005
  • (2004)Speculative software management of datapath-width for energy optimizationACM SIGPLAN Notices10.1145/998300.99717539:7(78-87)Online publication date: 11-Jun-2004
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