CADSS: Computer Architecture Design Simulator for Students
Pages 34 - 40
Abstract
Computer architecture is primarily studied through simulation. Most existing simulators are either comprehensive research tools, or ones targeting a single area within computer architecture. CADSS is an open source computer architecture simulator that can support simulations written in multiple languages across a variety of areas of computer architecture, either individually or combined together. It is designed to support student learning, as well as assessment by instructors.
References
[1]
[1] 2023. https://github.com/bprail/cadss_public
[2]
Nael Abu-Ghazaleh, Dmitry Ponomarev, and Dmitry Evtyushkin. 2019. How the spectre and meltdown hacks really worked. IEEE Spectrum 56, 3 (2019), 42–49. https://doi.org/10.1109/MSPEC.2019.8651934
[3]
Todd Austin, Eric Larson, and Dan Ernst. 2002. SimpleScalar: An infrastructure for computer system modeling. Computer 35, 2 (2002), 59–67.
[4]
Christian Bienia. 2011. Benchmarking Modern Multiprocessors. Ph. D. Dissertation. Princeton University.
[5]
Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The Gem5 Simulator. SIGARCH Comput. Archit. News 39, 2 (aug 2011), 1–7. https://doi.org/10.1145/2024716.2024718
[6]
Randal E. Bryant and David R. O’Hallaron. 2001. Introducing Computer Systems from a Programmer’s Perspective. In Proceedings of the Thirty-second SIGCSE Technical Symposium on Computer Science Education (Charlotte, North Carolina, USA) (SIGCSE ’01). ACM, New York, NY, USA, 90–94. https://doi.org/10.1145/364447.364549
[7]
Victoria Caparrós Cabezas. 2017. A DAG-Based Approach to Modeling Bottlenecks on Modern Microarchitectures. Ph. D. Dissertation. ETH Zurich.
[8]
Allen Chen, Deepak Souda Bhat, and Edward F. Gehringer. 2015. An Extensible Simulator for Bus- and Directory-Based Cache Coherence. In Proceedings of the Workshop on Computer Architecture Education (Portland, Oregon) (WCAE ’15). Association for Computing Machinery, New York, NY, USA, Article 2, 7 pages. https://doi.org/10.1145/2795122.2795124
[9]
Yu Chen and Hessam S. Sarjoughian. 2010. A Component-based Simulator for MIPS32 Processors. SIMULATION 86, 5-6 (2010), 271–290. https://doi.org/10.1177/0037549709346279
[10]
Roberto Giorgi and Gianfranco Mariotti. 2019. WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment. In Proceedings of the Workshop on Computer Architecture Education (Phoenix, AZ, USA) (WCAE’19). Association for Computing Machinery, New York, NY, USA, Article 3, 6 pages. https://doi.org/10.1145/3338698.3338894
[11]
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely, and Joel Emer. 2010. High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP). In Proceedings of the 37th Annual International Symposium on Computer Architecture (Saint-Malo, France) (ISCA ’10). Association for Computing Machinery, New York, NY, USA, 60–71. https://doi.org/10.1145/1815961.1815971
[12]
Peter Jamieson, Ricardo Ferreira, and José Augusto Nacif. 2021. Personalizing Online Computer Engineering Resources and Labs for Digital, Embedded, and Computer System Courses. In 2021 IEEE Frontiers in Education Conference (FIE). 1–5. https://doi.org/10.1109/FIE49875.2021.9637244
[13]
Daniel A Jiménez and Calvin Lin. 2001. Dynamic branch prediction with perceptrons. In Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture. IEEE, 197–206.
[14]
Di Xiang Lim and K G Smitha. 2019. Pipelined MIPS Simulation: A plug-in to MARS simulator for supporting pipeline simulation and branch prediction. In 2019 IEEE International Conference on Engineering, Technology and Education (TALE). 1–7. https://doi.org/10.1109/TALE48000.2019.9225934
[15]
Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. 2005. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation (Chicago, IL, USA) (PLDI ’05). ACM, New York, NY, USA, 190–200. https://doi.org/10.1145/1065010.1065034
[16]
Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE). 1–7. https://doi.org/10.1109/WCAE53984.2021.9707152
[17]
Scott McFarling. 1993. Combining branch predictors. Technical Report. Citeseer.
[18]
Joydeep Mitra. 2023. Studying the Impact of Auto-Graders Giving Immediate Feedback in Programming Assignments. In Proceedings of the 54th ACM Technical Symposium on Computer Science Education V. 1 (Toronto ON, Canada) (SIGCSE 2023). Association for Computing Machinery, New York, NY, USA, 388–394. https://doi.org/10.1145/3545945.3569726
[19]
Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P Jouppi. 2009. CACTI 6.0: A tool to model large caches. HP laboratories 27 (2009), 28.
[20]
Shien-Tai Pan, Kimming So, and Joseph T. Rahmeh. 1992. Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (Boston, Massachusetts, USA) (ASPLOS V). Association for Computing Machinery, New York, NY, USA, 76–84. https://doi.org/10.1145/143365.143490
[21]
Morten B. Petersen. 2021. Ripes: A Visual Computer Architecture Simulator. In 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE). 1–8. https://doi.org/10.1109/WCAE53984.2021.9707149
[22]
P. W. C. Prasad, Abeer Alsadoon, Azam Beg, and Anthony Chan. 2016. Using Simulators for Teaching Computer Organization and Architecture. Comput. Appl. Eng. Educ. 24, 2 (mar 2016), 215–224.
[23]
Zaharije Radivojevic, Zarko Stanisavljevic, and Marija Punt. 2018. Configurable simulator for computer architecture and organization. Computer Applications in Engineering Education 26, 5 (2018), 1711–1724.
[24]
Brian P. Railing, Eric R. Hein, and Thomas M. Conte. 2015. Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs. ACM Trans. Archit. Code Optim. 12, 2, Article 25 (July 2015), 24 pages. https://doi.org/10.1145/2776893
[25]
Carlos Salazar and Major Bobby Birrer. 2020. Instrumentation and Extension of reduced, simulated Single Cycle MIPS architecture to improve Student Comprehension. In 2020 IEEE Frontiers in Education Conference (FIE). 1–5. https://doi.org/10.1109/FIE44824.2020.9273938
[26]
Derek C. Schuurman. 2013. Step-by-Step Design and Simulation of a Simple CPU Architecture. In Proceeding of the 44th ACM Technical Symposium on Computer Science Education (Denver, Colorado, USA) (SIGCSE ’13). Association for Computing Machinery, New York, NY, USA, 335–340. https://doi.org/10.1145/2445196.2445296
[27]
André Seznec and Pierre Michaud. 2006. A case for (partially) TAgged GEometric history length branch prediction. The Journal of Instruction-Level Parallelism 8 (2006), 23.
[28]
John Paul Shen and Mikko H Lipasti. 2013. Modern processor design: fundamentals of superscalar processors. Waveland Press.
[29]
Arjun Singh, Sergey Karayev, Kevin Gutowski, and Pieter Abbeel. 2017. Gradescope: A Fast, Flexible, and Fair System for Scalable Assessment of Handwritten Work. In Proceedings of the Fourth (2017) ACM Conference on Learning @ Scale (Cambridge, Massachusetts, USA) (L@S ’17). Association for Computing Machinery, New York, NY, USA, 81–88. https://doi.org/10.1145/3051457.3051466
[30]
Ellen Spertus and Zachary Kurmas. 2021. Mastery-Based Learning in Undergraduate Computer Architecture. In 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE). 1–7. https://doi.org/10.1109/WCAE53984.2021.9707147
[31]
Sriseshan Srikanth, Brian P. Railing, and Thomas M. Conte. 2015. Dynamically Reconfiguring Multi-Core Architectures using Task Graph based Analysis. In Proceedings of the 24th International Conference on Parallel Architectures and Compilation(PACT ’15). ACM, New York, NY, USA.
[32]
Alexander Underwood and James E. Stine. 2019. An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education. In Proceedings of the Workshop on Computer Architecture Education (Phoenix, AZ, USA) (WCAE’19). Association for Computing Machinery, New York, NY, USA, Article 8, 8 pages. https://doi.org/10.1145/3338698.3338888
[33]
Kenneth Vollmar and Pete Sanderson. 2006. MARS: An Education-Oriented MIPS Assembly Language Simulator. In Proceedings of the 37th SIGCSE Technical Symposium on Computer Science Education (Houston, Texas, USA) (SIGCSE ’06). Association for Computing Machinery, New York, NY, USA, 239–243. https://doi.org/10.1145/1121341.1121415
[34]
Jun Wang, Jesse Beu, Sudhakar Yalamanchili, and Tom Conte. 2012. Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. In 2012 SC Companion: High Performance Computing, Networking Storage and Analysis. 472–476. https://doi.org/10.1109/SC.Companion.2012.67
[35]
Tse-Yu Yeh and Y.N. Patt. 1993. A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History. In Proceedings of the 20th Annual International Symposium on Computer Architecture. 257–266. https://doi.org/10.1109/ISCA.1993.698566
Index Terms
- CADSS: Computer Architecture Design Simulator for Students
Recommendations
Teaching computer architecture with a graphical PC simulator
ITiCSE '11: Proceedings of the 16th annual joint conference on Innovation and technology in computer science educationWe have developed a full system x86 simulator for teaching computer architecture, with graphical interfaces allowing the internal components of the simulated computer to be observed and modified at runtime, and utilities for designing and simulating ...
Green16: a frugal CPU architecture
SAICSIT '13: Proceedings of the South African Institute for Computer Scientists and Information Technologists ConferenceA novel computer architecture called Green16 is presented. Green16 is designed with frugal innovation principles, and offers a small but comprehensive instruction set. The design is pedagogically motivated and its instructions can be directly read by ...
A configurable MIPS simulator for teaching computer architecture
CATE '07: Proceedings of the 10th IASTED International Conference on Computers and Advanced Technology in EducationWe present Visual-MIPS, a new tool for MIPS processor simulation, which adds a new dimension to teaching of computer architecture. Unlike many available tools for MIPS processor simulation such as SPIM [1], visual MIPS is fully configurable and can be ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
June 2023
56 pages
ISBN:9798400702532
DOI:10.1145/3605507
Copyright © 2023 Owner/Author.
This work is licensed under a Creative Commons Attribution International 4.0 License.
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 26 June 2024
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed limited
Conference
ISCA '23
Sponsor:
ISCA '23: The 50th Annual International Symposium on Computer Architecture
June 17 - 21, 2023
FL, Orlando, USA
Acceptance Rates
Overall Acceptance Rate 9 of 10 submissions, 90%
Upcoming Conference
ISCA '25
- Sponsor:
- sigarch
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 181Total Downloads
- Downloads (Last 12 months)181
- Downloads (Last 6 weeks)49
Reflects downloads up to 27 Dec 2024
Other Metrics
Citations
View Options
View options
View or Download as a PDF file.
PDFeReader
View online with eReader.
eReaderHTML Format
View this article in HTML Format.
HTML FormatLogin options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in