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GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration

Authors:

Yuanqing Cheng,

Xiaowei LiAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 42, Pages 1 - 9

https://doi.org/10.1145/3508352.3549464

Published: 22 December 2022 Publication History

Abstract

2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs. Although it significantly reduces development costs by chiplet reuse, the design and fabrication of interposers also introduce additional high non-recurring engineering (NRE) costs and development cycles which might be prohibitive for application-specific designs having low volume.

To address this challenge, in this paper, we propose a reusable general interposer architecture (GIA) to amortize NRE costs and accelerate integration flows of interposers across different chiplet-based systems effectively. The proposed assembly-time configurable interposer architecture covers both active interposers and passive interposers considering diverse applications of 2.5D systems. The agile interposer integration is also facilitated by a novel end-to-end design automation framework to generate optimal system assembly configurations including the selection of chiplets, inter-chiplet network configuration, placement of chiplets, and mapping on GIA, which are specialized for the given target workload. The experimental results show that our proposed active GIA and passive GIA achieve 3.15x and 60.92x performance boost with 2.57x and 2.99x power saving over baselines respectively.

References

[1]

Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 2012. Architecture and CAD for deep-submicron FPGAs. Vol. 497.

Digital Library

[2]

Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, and Li-Shiuan Peh. 2013. SMART: A single-cycle reconfigurable NoC for SoC applications. In Design, Automation Test in Europe Conference Exhibition. 338--343.

[3]

Ayse Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Aditya Narayan, and Vaishnav Srinivas. 2020. Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 12 (2020), 5183--5196.

[4]

Robert P Dick, David L Rhodes, and Wayne Wolf. 1998. TGFF: task graphs for free. In Proceedings of the Sixth International Workshop on Hardware/Software Codesign. IEEE, 97--101.

[5]

Pete Ehrett, Todd Austin, and Valeria Bertacco. 2019. SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design. In Design, Automation Test in Europe Conference Exhibition. 510--515.

[6]

Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful Mojumder, and Tiansheng Zhang. 2018. Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. In Design, Automation Test in Europe Conference Exhibition. 1441--1446.

[7]

Yinxiao Feng and Kaisheng Ma. 2022. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration. arXiv preprint arXiv:2203.12268 (2022).

[8]

Ilya K Ganusov, Mahesh A Iyer, Ning Cheng, and Alon Meisler. 2020. Agilex^™ generation of intel® fpgas. In IEEE Hot Chips Symposium. IEEE Computer Society, 1--26.

[9]

J Hruska. 2018. As chip design costs skyrocket, 3nm process node is in jeopardy. ExtremeTech https://www.extremetech.com/computing/272096-3nm-process-node (22 June 2018) (2018).

[10]

Jingcao Hu and Radu Marculescu. 2005. Energy-and performance-aware mapping for regular NoC architectures. IEEE Transactions on computer-aided design of integrated circuits and systems 24, 4 (2005), 551--562.

Digital Library

[11]

Natalie Enright Jerger, Ajaykumar Kannan, Zimo Li, and Gabriel H. Loh. 2014. NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?. In Annual IEEE/ACM International Symposium on Microarchitecture. 458--470.

[12]

Natalie Enright Jerger and Li-Shiuan Peh. 2009. On-chip networks. Synthesis Lectures on Computer Architecture 4, 1 (2009), 1--141.

[13]

Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, D. E. Shaw, John Kim, and William J. Dally. 2013. A detailed and flexible cycle-accurate Network-on-Chip simulator. In IEEE International Symposium on Performance Analysis of Systems and Software. 86--96.

[14]

Jukka Jylänki. 2010. A thousand ways to pack the bin-a practical approach to two-dimensional rectangle bin packing. http://clb.demon.fi/files/RectangleBinPack.pdf (2010).

[15]

Ajaykumar Kannan, Natalie Enright Jerger, and Gabriel H. Loh. 2015. Enabling interposer-based disintegration of multi-core processors. In Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 546--558.

[16]

Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, and Todd Austin. 2007. Architectural implications of brick and mortar silicon manufacturing. In Proceedings of the 34th annual international symposium on Computer architecture. 244--253.

Digital Library

[17]

Yenai Ma, Leila Delshadtehrani, Cansu Demirkiran, José L. Abellan, and Aiav Joshi. 2021. TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems. In Design, Automation Test in Europe Conference Exhibition. 1246--1251.

[18]

Radu Marculescu, Jingcao Hu, and Umit Y. Ogras. 2005. Key research problems in NoC design: a holistic perspective. In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 69--74.

[19]

Peter Moon, Vinay Chikarmane, Kevin Fischer, Rohit Grover, Tarek A Ibrahim, Doug Ingerly, Kevin J Lee, Chris Litteken, Tony Mule, and Sarah Williams. 2008. Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation. Intel Technology Journal 12, 2 (2008).

[20]

Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, and Luigi Raffo. 2006. Designing Application-Specific Networks on Chips with Floorplan Information. In IEEE/ACM International Conference on Computer Aided Design. 355--362.

[21]

Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, and Sean White. 2021. Pioneering Chiplet Technology and Design for the AMD EPYC^™ and Ryzen^™ Processor Families : Industrial Product. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture. 57--70.

Digital Library

[22]

Jawad Nasrullah, Zhiquan Luo, and Greg Taylor. 2019. Designing Software Configurable Chips and SIPs using Chiplets and zGlue. In International Symposium on Microelectronics, Vol. 2019. International Microelectronics Assembly and Packaging Society, 27--32.

[23]

Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, and Puneet Gupta. 2021. Designing a 2048-Chiplet, 14336-Core Waferscale Processor. In ACM/IEEE Design Automation Conference. 1183--1188.

Digital Library

[24]

Heechun Park, Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Majid Ahadi Dolatsara, Mohammed Nabeel, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay, Johann Knechtel, and Sung Kyu Lim. 2020. Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISCV Architecture With Secure NoC. IEEE Transactions on Components, Packaging and Manufacturing Technology 10, 12 (2020), 2047--2060.

[25]

Uneeb Rathore, Sumeet Singh Nagi, Subramanian Iyer, and Dejan Marković. 2022. A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2x2 Dielet with 10um-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration. In IEEE International Solid- State Circuits Conference, Vol. 65. 52--54.

[26]

David Starobinski, Mark Karpovsky, and Lev A Zakrevski. 2003. Application of network calculus to general topologies using turn-prohibition. IEEE/ACM Transactions on Networking 11, 3 (2003), 411--421.

Digital Library

[27]

Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu, and Yuan Xie. 2016. Cost Analysis and Cost-Driven IP Reuse Methodology for SoC Design Based on 2.5D/3D Integration. In Proceedings of the 35th International Conference on Computer-Aided Design. Article 56, 6 pages.

Digital Library

[28]

Dylan Stow, Itir Akgun, and Yuan Xie. 2019. Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In ACM/IEEE International Workshop on System Level Interconnect Prediction. 1--8.

[29]

Dylan Stow, Yuan Xie, Taniya Siddiqua, and Gabriel H. Loh. 2017. Cost-effective design of scalable high-performance systems using active and passive interposers. In IEEE/ACM International Conference on Computer-Aided Design. 728--735.

[30]

Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, and Vladimir Stojanovic. 2012. DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In IEEE/ACM Sixth International Symposium on Networks-on-Chip. 201--210.

Digital Library

[31]

Yifan Sun, Nicolas Bohm Agostini, Shi Dong, and David Kaeli. 2019. Summarizing CPU and GPU design trends with product data. arXiv preprint arXiv:1911.11313 (2019).

[32]

TechPowerUp. 2022. NVIDIA GeForce GT 1010. https://www.techpowerup.com/gpu-specs/geforce-gt-1010.c3762#:~:text=The%20GeForce%20GT%201010%20was,run%20on%20GeForce%20GT%201010.

[33]

P Vivet et al. 2020. A 220GOPS 96-core processor with 6 chiplets 3D-stacked on an active interposer offering 0.6 ns/mm latency, 3TBit/s/mm2 inter-chiplet interconnects and 156mW/mm2@ 82% Peak-Efficiency DC-DC Converters. In Proc. IEEE Int. Conf. Solid-State Circuits.

[34]

Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita Das, and Jian Li. 2010. Cost-Driven 3D Integration with Interconnect Layers. In Proceedings of the 47th Design Automation Conference. 150--155.

Digital Library

[35]

Jing Xia, Chuanning Cheng, Xiping Zhou, Yuxing Hu, and Peter Chun. 2021. Kunpeng920: The First7-nm Chiplet-Based 64-Core ARM SoC for Cloud Services. IEEE Micro 41, 5 (2021), 67--75.

Digital Library

[36]

Lilia Zaourar, Massinissa Ait Aba, David Briand, and Jean-Marc Philippe. 2017. Modeling of Applications and Hardware to Explore Task Mapping and Scheduling Strategies on a Heterogeneous Micro-Server System. In IEEE International Parallel and Distributed Processing Symposium Workshops. 65--76.

[37]

Runjie Zhang, Mircea R Stan, and Kevin Skadron. 2015. Hotspot 6.0: Validation, acceleration and extension. University of Virginia, Tech. Rep (2015).

Cited By

Chen SLi SZhuang ZZheng SLiang ZHo TYu BSangiovanni-Vincentelli A(2024)Floorplet: Performance-Aware Floorplan Framework for Chiplet IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334730243:6(1638-1649)Online publication date: Jun-2024
https://doi.org/10.1109/TCAD.2023.3347302
Biglari SHosseini FUpadhyay AZhao H(2024)Survey of Network-on-Chip (NoC) for Heterogeneous Multicore Systems2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC64144.2024.00036(155-162)Online publication date: 16-Dec-2024
https://doi.org/10.1109/MCSoC64144.2024.00036
Liu YLi XYin S(2024)Review of chiplet-based design: system architecture and interconnectionScience China Information Sciences10.1007/s11432-023-3926-867:10Online publication date: 19-Jul-2024
https://doi.org/10.1007/s11432-023-3926-8
Show More Cited By

Index Terms

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration
1. Computer systems organization
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Index terms have been assigned to the content through auto-classification.

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Information

Published In

cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

Copyright © 2022 Owner/Author.

This work is licensed under a Creative Commons Attribution International 4.0 License.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE-EDS: Electronic Devices Society
IEEE CAS
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 December 2022

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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

October 30 - November 3, 2022

California, San Diego

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Chen SLi SZhuang ZZheng SLiang ZHo TYu BSangiovanni-Vincentelli A(2024)Floorplet: Performance-Aware Floorplan Framework for Chiplet IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334730243:6(1638-1649)Online publication date: Jun-2024
https://doi.org/10.1109/TCAD.2023.3347302
Biglari SHosseini FUpadhyay AZhao H(2024)Survey of Network-on-Chip (NoC) for Heterogeneous Multicore Systems2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC64144.2024.00036(155-162)Online publication date: 16-Dec-2024
https://doi.org/10.1109/MCSoC64144.2024.00036
Liu YLi XYin S(2024)Review of chiplet-based design: system architecture and interconnectionScience China Information Sciences10.1007/s11432-023-3926-867:10Online publication date: 19-Jul-2024
https://doi.org/10.1007/s11432-023-3926-8
Sharma HPfromm LTopaloglu RDoppa JOgras UKalyanraman APande P(2023)Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference TasksACM Transactions on Embedded Computing Systems10.1145/360809822:5s(1-21)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608098
Hao XDing ZYin JWang YLiang Y(2023)Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323880(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323880

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