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research-article

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility

Authors:

Yibo LinAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 649 - 654

https://doi.org/10.1145/3489517.3530568

Published: 23 August 2022 Publication History

Abstract

Modern field-programmable gate arrays (FPGAs) contain heterogeneous resources, including CLB, DSP, BRAM, IO, etc. A Configurable Logic Block (CLB) slice is further categorized to SLICEL and SLICEM, which can be configured as specific combinations of instances in {LUT, FF, distributed RAM, SHIFT, CARRY}. Such kind of heterogeneity challenges the existing FPGA placement algorithms. Meanwhile, limited clock routing resources also lead to complicated clock constraints, causing difficulties in achieving clock feasible placement solutions. In this work, we propose a heterogeneous FPGA placement framework considering SLICEL-SLICEM heterogeneity and clock feasibility based on a multi-electrostatic formulation. We support a comprehensive set of the aforementioned instance types with a uniform algorithm for wirelength, routability, and clock optimization. Experimental results on both academic and industrial benchmarks demonstrate that we outperform the state-of-the-art placers in both quality and efficiency.

References

[1]

S. Chen and Y. Chang, "Routing-architecture-aware analytical placement for heterogeneous fpgas," in Proc. DAC. ACM, 2015, pp. 27:1--27:6.

[2]

W. Li, S. Dhar, and D. Z. Pan, "Utplacef: A routability-driven FPGA placer with physical and congestion aware packing," IEEE TCAD, vol. 37, no. 4, pp. 869--882, 2018.

[3]

C. Pui, G. Chen, W. Chow, K. Lam, J. Kuang, P. Tu, H. Zhang, E. F. Y. Young, and B. Yu, "Ripplefpga: a routability-driven placement for large-scale heterogeneous fpgas," in Proc. ICCAD, 2016, p. 67.

Digital Library

[4]

R. Pattison, Z. Abuowaimer, S. Areibi, G. Gréwal, and A. Vannelli, "Gplace: a congestion-aware placement tool for ultrascale fpgas," in Proc. ICCAD, 2016, p. 68.

Digital Library

[5]

W. Li and D. Z. Pan, "A new paradigm for FPGA placement without explicit packing," IEEE TCAD, vol. 38, no. 11, pp. 2113--2126, 2019.

[6]

W. Li, Y. Lin, M. Li, S. Dhar, and D. Z. Pan, "Utplacef 2.0: A high-performance clock-aware FPGA placement engine," ACM TODAES, vol. 23, no. 4, pp. 42:1--42:23, 2018.

Digital Library

[7]

W. Li, M. E. Dehkordi, S. Yang, and D. Z. Pan, "Simultaneous placement and clock tree construction for modern fpgas," in Proc. FPGA, 2019, pp. 132--141.

[8]

C. Pui, G. Chen, Y. Ma, E. F. Y. Young, and B. Yu, "Clock-aware ultrascale FPGA placement with machine learning routability prediction: (invited paper)," in Proc. ICCAD. IEEE, 2017, pp. 929--936.

[9]

T. Liang, G. Chen, J. Zhao, L. Feng, S. Sinha, and W. Zhang, "Amf-placer: High-performance analytical mixed-size placer for fpga," in Proc. ICCAD, 2021, pp. 1--6.

Digital Library

[10]

Y. Meng, W. Li, Y. Lin, and D. Z. Pan, "elfplace: Electrostatics-based placement for large-scale heterogeneous fpgas," IEEE TCAD, 2021.

[11]

Y. Kuo, C. Huang, S. Chen, C. Chiang, Y. Chang, and S. Kuo, "Clock-aware placement for large-scale heterogeneous fpgas," in Proc. ICCAD, 2017, pp. 519--526.

[12]

J. Chen, Z. Lin, Y. Kuo, C. Huang, Y. Chang, S. Chen, C. Chiang, and S. Kuo, "Clock-aware placement for large-scale heterogeneous fpgas," IEEE TCAD, vol. 39, no. 12, pp. 5042--5055, 2020.

[13]

G. Chen, C.-W. Pui, W.-K. Chow, K.-C. Lam, J. Kuang, E. F. Young, and B. Yu, "RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs," IEEE TCAD, vol. 37, no. 10, pp. 2022--2035, 2018.

[14]

Z. Abuowaimer, D. Maarouf, T. Martin, J. Foxcroft, G. Gréwal, S. Areibi, and A. Vannelli, "GPlace3.0: Routability-driven analytic placer for UltraScale FPGA architectures," ACM TODAES, vol. 23, no. 5, pp. 66:1--66:33, 2018.

Digital Library

[15]

Ultrascale architecture clb slices. [Online]. Available: https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf

[16]

S. Yang, C. Mulpuri, S. Reddy, M. Kalase, S. Dasasathyan, M. E. Dehkordi, M. Tom, and R. Aggarwal, "Clock-aware FPGA placement contest," in Proc. ISPD, 2017, pp. 159--164.

[17]

Ultrascale architecture clocking resources. [Online]. Available: https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

[18]

S. Yang, A. Gayasen, C. Mulpuri, S. Reddy, and R. Aggarwal, "Routability-driven FPGA placement contest," in Proc. ISPD, 2016, pp. 139--143.

Digital Library

[19]

J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, "ePlace: Electrostatics-based placement using fast fourier transform and nesterov's method," ACM TODAES, vol. 20, no. 2, p. 17, 2015.

Digital Library

[20]

J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng et al., "ePlace-MS: Electrostatics-based placement for mixed-size circuits," IEEE TCAD, vol. 34, no. 5, pp. 685--698, 2015.

[21]

R. Andreani, E. G. Birgin, J. M. Martínez, and M. L. Schuverdt, "On augmented lagrangian methods with general lower-level constraints," SIAM Journal on Optimization, vol. 18, no. 4, pp. 1286--1309, 2008.

Digital Library

[22]

C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, "Replace: Advancing solution quality and routability validation in global placement," IEEE TCAD, 2018.

[23]

Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, "DREAMPlace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement," IEEE TCAD, June 2020.

Cited By

Di ZTao RChen LWu QLin Y(2024)Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing PredictionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.333424771:4(2034-2038)Online publication date: Apr-2024
https://doi.org/10.1109/TCSII.2023.3334247
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Kariotis KDadaliaris AKranas GDimitriou GDossis M(2024)Current Status of Analytical FPGA Placement2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM63478.2024.00015(30-35)Online publication date: 20-Sep-2024
https://doi.org/10.1109/SEEDA-CECNSM63478.2024.00015
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 23 August 2022

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111 Project
National Science Foundation of China

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DAC '22

Sponsor:

SIGDA

DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Di ZTao RChen LWu QLin Y(2024)Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing PredictionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.333424771:4(2034-2038)Online publication date: Apr-2024
https://doi.org/10.1109/TCSII.2023.3334247
Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Kariotis KDadaliaris AKranas GDimitriou GDossis M(2024)Current Status of Analytical FPGA Placement2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM63478.2024.00015(30-35)Online publication date: 20-Sep-2024
https://doi.org/10.1109/SEEDA-CECNSM63478.2024.00015
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Luo QZang XWang QWang FYoung EWong M(2024)A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM60383.2024.00024(1-7)Online publication date: 5-May-2024
https://doi.org/10.1109/FCCM60383.2024.00024
Zhu ZMei YDeng KHe HChen JYang JChang Y(2023)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: 6-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3329774
Mai JWang JDi ZLin Y(2023)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: 7-Sep-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3313101
Jiang XGuo ZChai ZZhao YLin YWang RHuang R(2023)Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323938(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323938
Mai JWang JDi ZLuo GLiang YLin Y(2023)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396248(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396248

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