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Constructive library-aware synthesis using symmetries

Authors:

Victor N. Kravets,

Karem A. SakallahAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 208 - 215

https://doi.org/10.1145/343647.343734

Published: 01 January 2000 Publication History

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References

[1]

L. Benini, P. Vuillod, and G. De Micheli. Iterative re-mapping for logic circuits. IEEE TCAD IC, CAD-17(10):948- 964, October 1998.

Digital Library

Google Scholar

[2]

F.M. Brown. Boolean Reasoning. Kluwer Academic Publishers, Boston, 1990.

Google Scholar

[3]

R.E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE TC, C-35(6):677-691, August 1986.

Digital Library

Google Scholar

[4]

D.L. Dietmeyer and P. Schneider. Identification of symmetry, redundancy and equivalence of boolean functions. IEEE TEC, EC-16(6):804-807, December 1967.

Crossref

Google Scholar

[5]

C.R.Edwards andS. L. Hurst. Adigital synthesis procedure under function symmetries and mapping methods. IEEE TC, C-27:985-997, 1978.

Digital Library

Google Scholar

[6]

B.-G. Kim and D. L. Dietmeyer. Multilevel logic synthesis of symmetric switching functions. IEEE TCAD IC, 10(4):436-446, April 1991.

Crossref

Google Scholar

[7]

W. Kunz and D. Stoffel. Reasoning in Boolean Networks. Kluwer Academic Publishers, 1997.

Digital Library

Google Scholar

[8]

Y.T. Lai, M. Pedram, and Sarma B. K. Vrudhula. B DD based decomposition of logic functions with application to FPGA synthesis. In Proc. 30th DAC, pages 642-647, June 1993.

Digital Library

Google Scholar

[9]

E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness. Logic decomposition during technology mapping. In Proc. Int. Conf. Computer Design, pages 263-271, 1995.

Digital Library

Google Scholar

[10]

D. Moller, J. Mohnke, andM. Weber. Detection ofsymmetry of boolean functions represented by ROBDDs. In Proc. ICCAD, pages 680-684, October 1993.

Digital Library

Google Scholar

[11]

R. Murgai, R. K. Brayton, and A. Sangiovanni-Vincentelli. Optimum functional decompositions using encoding. In Proc. 31st DAC, pages 408-414, June 1994.

Digital Library

Google Scholar

[12]

J.P. Roth and R. Karp. Minimization over boolean graphs. IBM J. Res. and Develop., 6(2):227-238, April 1962.

Digital Library

Google Scholar

[13]

H. Sawada, T. Suyama, andA. Nagoya. Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. In IEEE ICCAD, pages 353-358, November 1995.

Digital Library

Google Scholar

[14]

H. Sawada, S. Yamashita, and A. Nagoya. Restructuring logic representations with easily detectable simple disjunctive decompositions. In DATE, pages 755-759, February 1998.

Digital Library

Google Scholar

[15]

C. Scholl, D. Moiler, P. Molitor, and R. Drechsler. BDD minimization using symmetries. IEEE TCAD IC, 18(2):81- 100, February 1999.

Digital Library

Google Scholar

[16]

E.M. Sentovich. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, UC Berkeley, May 1992.

Google Scholar

[17]

F. Somenzi. CUDD: CU Decision Diagram Package. University of Colorado, Boulder, 2.1.2 edition, April 1997.

Google Scholar

[18]

B. Wurth, K. Eckl, and K. Antreich. Functional multipleoutput decomposition: theory and an implicit algorithm. In Proc. 32nd DAC, pages 54-59, June 1995.

Digital Library

Google Scholar

[19]

S. Yang. Logic synthesis and optimization benchmarks user guide- vet. 3.0. MCNC, Res. Triangle Park, NC, Jan. 1991.

Google Scholar

Cited By

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Bernasconi ACiriani V(2021)Autosymmetry of Incompletely Specified Functions2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474138(360-365)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474138
Chu ZSoeken MXia YWang LDe Micheli G(2020)Advanced Functional Decomposition Using Majority and Its ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292539239:8(1621-1634)Online publication date: Aug-2020
https://doi.org/10.1109/TCAD.2019.2925392
Sasao T(2019)Index Generation FunctionsSynthesis Lectures on Digital Circuits and Systems10.2200/S00953ED1V01Y201909DCS05714:3(1-183)Online publication date: 24-Oct-2019
https://doi.org/10.2200/S00953ED1V01Y201909DCS057
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Index Terms

Constructive library-aware synthesis using symmetries
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 2000

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DATE00: Design Automation and Test in Europe

March 27 - 30, 2000

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Cited By

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Bernasconi ACiriani V(2021)Autosymmetry of Incompletely Specified Functions2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474138(360-365)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474138
Chu ZSoeken MXia YWang LDe Micheli G(2020)Advanced Functional Decomposition Using Majority and Its ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292539239:8(1621-1634)Online publication date: Aug-2020
https://doi.org/10.1109/TCAD.2019.2925392
Sasao T(2019)Index Generation FunctionsSynthesis Lectures on Digital Circuits and Systems10.2200/S00953ED1V01Y201909DCS05714:3(1-183)Online publication date: 24-Oct-2019
https://doi.org/10.2200/S00953ED1V01Y201909DCS057
Chu ZSoeken MXia YDe Micheli GShin Y(2018)Functional decomposition using majorityProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201762(676-681)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201762
Chu ZSoeken MXia YDe Micheli G(2018)Functional decomposition using majority2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297400(676-681)Online publication date: Jan-2018
https://doi.org/10.1109/ASPDAC.2018.8297400
Sasao TMatsuura KIguchi Y(2017)An algorithm to find optimum support-reducing decompositions for index generation functionsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130575(812-817)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130575
Sasao TMatsuura KIguchi Y(2017)An algorithm to find optimum support-reducing decompositions for index generation functionsDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927100(812-817)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927100
Sasao TButler J(2017)Decomposition of Index Generation Functions Using a Monte Carlo MethodAdvanced Logic Synthesis10.1007/978-3-319-67295-3_10(209-225)Online publication date: 16-Nov-2017
https://doi.org/10.1007/978-3-319-67295-3_10
Mishchenko AEen NBrayton RCase MChauhan PSharma NMacii E(2013)A semi-canonical form for sequential AIGsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485481(797-802)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485481
Maurer PBrunvard EStevens KCavallaro JZhang T(2012)Extending symmetric variable-pair transitivities using state-space transformationsProceedings of the great lakes symposium on VLSI10.1145/2206781.2206859(315-320)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206859
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