Aiming to decrease the hardware cost of floating-point quadruple precision fused multiply-add (QPFMA) unit, a new QPFMA unit is designed and realized based on a 4-way SIMD device, which supports 64-bit 4 floating-point double precision fused multiply-...
A new floating-point fused multiply-add (FMA) design for the execution of (A × B)+C as a single instruction is presented. The bridge fused multiply-add unit is a design intended to add FMA functionality to existing floating-point coprocessor units by ...
Various features found in standard floating point arithmetic (IEEE 754) are examined in light of their appropriateness for sign/logarithm arithmetic. The emphasis is on a 32-b word size comparable to IEEE 754 single precision, although other word sizes ...
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