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NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs

Authors:

Yuan XieAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 17, Issue 4

Article No.: 31, Pages 1 - 25

https://doi.org/10.1145/3417709

Published: 10 November 2020 Publication History

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Abstract

The tremendous impact of deep learning algorithms over a wide range of application domains has encouraged a surge of neural network (NN) accelerator research. Facilitating the NN accelerator design calls for guidance from an evolving benchmark suite that incorporates emerging NN models. Nevertheless, existing NN benchmarks are not suitable for guiding NN accelerator designs. These benchmarks are either selected for general-purpose processors without considering unique characteristics of NN accelerators or lack quantitative analysis to guarantee their completeness during the benchmark construction, update, and customization.

In light of the shortcomings of prior benchmarks, we propose a novel benchmarking methodology for NN accelerators with a quantitative analysis of application performance features and a comprehensive awareness of software-hardware co-design. Specifically, we decouple the benchmarking process into three stages: First, we characterize the NN workloads with quantitative metrics and select the representative applications for the benchmark suite to ensure diversity and completeness. Second, we refine the selected applications according to the customized model compression techniques provided by specific software-hardware co-design. Finally, we evaluate a variety of accelerator designs on the generated benchmark suite. To demonstrate the effectiveness of our benchmarking methodology, we conduct a case study of composing an NN benchmark from the TensorFlow Model Zoo and compress these selected models with various model compression techniques. Finally, we evaluate compressed models on various architectures, including GPU, Neurocube, DianNao, and Cambricon-X.

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Cited By

Kljucaric LGeorge A(2023)Deep Learning Inferencing with High-performance Hardware AcceleratorsACM Transactions on Intelligent Systems and Technology10.1145/359422114:4(1-25)Online publication date: 15-Jun-2023
https://dl.acm.org/doi/10.1145/3594221
Smagulova KFouda MKurdahi FSalama KEltawil A(2023)Resistive Neural Hardware AcceleratorsProceedings of the IEEE10.1109/JPROC.2023.3268092111:5(500-527)Online publication date: May-2023
https://doi.org/10.1109/JPROC.2023.3268092

Index Terms

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 17, Issue 4

December 2020

430 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3427420

Editor:
David Kaeli
Northeastern University, USA

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Publication History

Published: 10 November 2020

Accepted: 01 August 2020

Revised: 01 July 2020

Received: 01 October 2019

Published in TACO Volume 17, Issue 4

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Cited By

Kljucaric LGeorge A(2023)Deep Learning Inferencing with High-performance Hardware AcceleratorsACM Transactions on Intelligent Systems and Technology10.1145/359422114:4(1-25)Online publication date: 15-Jun-2023
https://dl.acm.org/doi/10.1145/3594221
Smagulova KFouda MKurdahi FSalama KEltawil A(2023)Resistive Neural Hardware AcceleratorsProceedings of the IEEE10.1109/JPROC.2023.3268092111:5(500-527)Online publication date: May-2023
https://doi.org/10.1109/JPROC.2023.3268092

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