research-article

Security analysis of logic obfuscation

Authors:

Jeyavijayan Rajendran,

Youngok Pino,

Ozgur Sinanoglu,

Ramesh KarriAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 83 - 89

https://doi.org/10.1145/2228360.2228377

Published: 03 June 2012 Publication History

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Abstract

Due to globalization of Integrated Circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware trojans. EPIC [1] obfuscates the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the obfuscated netlist, in a time linear to the number of keys, by sensitizing the key values to the output. We then develop techniques to fix this vulnerability and make obfuscation truly exponential in the number of inserted keys.

References

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Cited By

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Edwards AHassan NArzate JChin ABhattacharya DShihab MZhou PHu XAtulasimha JMakris YFriedman J(2025)Physically Secure Logic Locking With Nanomagnet LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343436244:1(105-118)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3434362
YOSHIMURA MTSUJIKAWA AHOSOKAWA T(2024)CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer LevelIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2023VLP0018E107.A:3(583-591)Online publication date: 1-Mar-2024
https://doi.org/10.1587/transfun.2023VLP0018
Zhang NWang KHuang K(2024)SFLL-AD: a self-adaptive and secure logic lockingIEICE Electronics Express10.1587/elex.20.2023055521:3(20230555-20230555)Online publication date: 10-Feb-2024
https://doi.org/10.1587/elex.20.20230555
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Index Terms

Security analysis of logic obfuscation
1. Security and privacy
2. Social and professional topics
  1. Computing / technology policy
    1. Computer crime

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Information & Contributors

Information

Published In

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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Research-article

Funding Sources

Air Force Research Laboratory

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DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Edwards AHassan NArzate JChin ABhattacharya DShihab MZhou PHu XAtulasimha JMakris YFriedman J(2025)Physically Secure Logic Locking With Nanomagnet LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343436244:1(105-118)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3434362
YOSHIMURA MTSUJIKAWA AHOSOKAWA T(2024)CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer LevelIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2023VLP0018E107.A:3(583-591)Online publication date: 1-Mar-2024
https://doi.org/10.1587/transfun.2023VLP0018
Zhang NWang KHuang K(2024)SFLL-AD: a self-adaptive and secure logic lockingIEICE Electronics Express10.1587/elex.20.2023055521:3(20230555-20230555)Online publication date: 10-Feb-2024
https://doi.org/10.1587/elex.20.20230555
Hashemi MMohammadi SCarlson T(2024)SRLL: Improving Security and Reliability with User-Defined Constraint-Aware Logic LockingACM Journal on Emerging Technologies in Computing Systems10.1145/3709139Online publication date: 23-Dec-2024
https://doi.org/10.1145/3709139
Sharma SRoy DPawar D(2024)PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/370103230:1(1-34)Online publication date: 17-Oct-2024
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McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
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Karmakar PBharani MKarfa C(2024)Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00092(517-522)Online publication date: 6-Jan-2024
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Rajendran SFarahmandi FTehranipoor M(2024)CAD Tools Pathway in Hardware Security2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00063(342-347)Online publication date: 6-Jan-2024
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Sarojam Chellam MNatarajan RNaganathan N(2024)Secure key exchange protocol and storage of logic locking key2024 28th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT63601.2024.10705695(1-6)Online publication date: 1-Sep-2024
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Vega CSLPSK PBhunia S(2024)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering AttacksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333731032:2(347-360)Online publication date: 1-Feb-2024
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Security analysis of integrated circuit camouflaging

IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview

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