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Register allocation and binding for low power

Authors:

Jui-Ming Chang,

Massoud PedramAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 29 - 35

https://doi.org/10.1145/217474.217502

Published: 01 January 1995 Publication History

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References

[1]

M. Balakrishnan and P. Marwedel. "Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration". In proc. of the 26th ACM/IEEE DAC, pp. 68-74, 1989.]]

Digital Library

Google Scholar

[2]

J-M. Chang, M. Pedram,"Power Efficient Register Assignment", CENG Technical Report 95-03, University of Southern California, Mar. 1995.]]

Google Scholar

[3]

G. De Micheli,"Synthesis and Optimization of Digital Circuits" ', McGraw Hill 1994.]]

Digital Library

Google Scholar

[4]

J. Edmonds and R.M. Karp,"Theoretical Improvements in Algorithmic Efficiency for Network Flow Problems", Journal of the ACM, vol 19, no2, pp 248-264, April 1972.]]

Digital Library

Google Scholar

[5]

M.C.Golumbic, "Algorithmic Graph Theory and Perfect Graphs", Academic Press 1980.]]

Digital Library

Google Scholar

[6]

G. Goossens, D Lanneer, J. Vanhoof, J Rabaey, J. Van Meerbergen, and H. De Man. "Optimization-Based Synthesis of Multiprocessor Chips for Digital Signal Processing with Cathedral- II". In G. Saucier and P.M. McLellan, editor, Logic and Architecture Synthesis, 1988.]]

Google Scholar

[7]

C.Y. Hitchcock and D.E. Thomas, "A Method of Automatic Data Path Synthesis", in Proc. of the 20th Design Automatic Conf. New York, NY:ACM/IEEE, pp. 484-489, June 1983.]]

Digital Library

Google Scholar

[8]

R. Hogg, A. Craig, "Introduction to Mathematical Statistics". fourth Edition. pp.147-152.]]

Google Scholar

[9]

D. Ku, G. De Micheli, "Relative Scheduling Under Timing Constraints", in DAC, Proceedings of Design Automation Conference, pp. 59-64, June 1990.]]

Digital Library

Google Scholar

[10]

K. Kiiciikcakar and A. Parker. "MABAL, A Software Package for Module and Bus Allocation". International Journal of Computer Aided VLSI Design, pp. 419-436, 1990.]]

Google Scholar

[11]

F. Kurdahi, A. Parker, "REAL: A Program for REgister Allocation", in Proceeding of 24th Design Automation Conference, June 1987.]]

Digital Library

Google Scholar

[12]

P. Michel, U. Lauther, P. Duzy, "The Synthesis Approach to Digital System Design", Kluwer Academic Publishers.]]

Digital Library

Google Scholar

[13]

B.M. Pangrle and D.D Gaski, "Design Tools for Intelligent Silicon Compilation", IEEE trans, on CAD, 6(6), Nov. 1987.]]

Google Scholar

[14]

C. Papadimitriou, K. Steiglitz, "Combinatorial Optimization, Algorithms and Complexity". Prentice-Hall, inc., 1982.]]

Digital Library

Google Scholar

[15]

A. Papoulis, "Probability, Random Variables, and Stochastic Processes". Third Edition, section 6.3, McGraw-Hill, 1991.]]

Google Scholar

[16]

P.G. Paulin and J.P. Knight, "Scheduling and Binding Algorithms for High-Level Synthesis", in Proc. of the 26th ACM/IEEE Design Automation Conference (DAC), page 1-6, 1989.]]

Digital Library

Google Scholar

[17]

L. Stok,"An Exact Polynomial Time Algorithm for Module Allocation", in Fifth International Workshop on High-Level Synthesis, Biihlerh6he, pp.69-76, March 3-9 1991.]]

Google Scholar

[18]

C.-J. Tseng and D.P. Siewiorek, "Automated Synthesis of Data Paths in Digital Systems", IEEE trans, on CAD, 5(3), July 1986.]]

Google Scholar

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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DAC95: The 32nd Design Automation Conference

June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Choi JShull TGarzaran MTorrellas J(2017)ShortCutACM SIGARCH Computer Architecture News10.1145/3140659.308023745:2(494-506)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080237
Gope DSchlais DLipasti M(2017)Architectural Support for Server-Side PHP ProcessingACM SIGARCH Computer Architecture News10.1145/3140659.308023445:2(507-520)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080234
Kolli AGogte VSaidi ADiestelhorst SChen PNarayanasamy SWenisch T(2017)Language-level persistencyACM SIGARCH Computer Architecture News10.1145/3140659.308022945:2(481-493)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080229
Lin CHuang CKuan CHuang SLee J(2015)The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore SystemsACM Transactions on Design Automation of Electronic Systems10.1145/269983420:2(1-27)Online publication date: 2-Mar-2015
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Luna MSilva FAttrot W(2015)Decreasing Spill Code to Decrease Energy ConsumptionProceedings of the 2015 Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2015.31(128-131)Online publication date: 3-Nov-2015
https://dl.acm.org/doi/10.1109/SBESC.2015.31
Lin CKuan CShih WLee J(2015)Compilers for Low Power with Design Patterns on Embedded Multicore SystemsJournal of Signal Processing Systems10.1007/s11265-014-0917-980:3(277-293)Online publication date: 1-Sep-2015
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Shih WYou YHuang CLee J(2014)Compiler Optimization for Reducing Leakage Power in Multithread BSP ProgramsACM Transactions on Design Automation of Electronic Systems10.1145/266811920:1(1-34)Online publication date: 18-Nov-2014
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Chen LTahoori M(2014)Reliability-aware Register Binding for Control-Flow Intensive DesignsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593200(1-6)Online publication date: 1-Jun-2014
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Bhuvaneswari MHarish Ram DNeelaveni R(2014)Design Space Exploration for Scheduling and Allocation in High Level Synthesis of DatapathsApplication of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems10.1007/978-81-322-1958-3_5(69-92)Online publication date: 17-Jul-2014
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Xydis SPalermo GSilvano CMacii E(2013)Thermal-aware datapath merging for coarse-grained reconfigurable processorsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485679(1649-1654)Online publication date: 18-Mar-2013
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