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A New Metric to Measure Cache Utilization for HPC Workloads

Published: 03 October 2016 Publication History

Abstract

High performance computing (HPC) systems continue to add cores and memory to keep pace with increases in data processing needs, resulting in increased data movement across the memory hierarchy. With these systems becoming more and more energy constrained, data movement costs in terms of energy and performance cannot be neglected. Conventional techniques for modeling and analyzing data movement across the memory hierarchy have proven to be inadequate in helping computer architects and system designers to optimize data movement. In this work, we present modeling approaches to help capture and better understand cache utilization in the various levels of the memory hierarchy. We define a new metric, average cache references per evictions (ACRE), as a measure of cache utilization. We observed that the ACRE values for L1 cache varies from 18 to 210 for Mantevo miniapps and from 11 to 55 for GraphBIG benchmarks. ACRE values for L2/L3 caches were observed to be around 1 for all benchmarks. Such cache utilization metrics provide more meaningful insights about the data movement occurring across the memory hierarchy, enabling computer architects and system designers to better manage and minimize data movement and in turn reduce energy and even improve performance.

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Cited By

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  • (2018)A performance study of the time-varying cache behaviorThe Journal of Supercomputing10.1007/s11227-017-2144-174:2(665-695)Online publication date: 1-Feb-2018
  • (2017)Using data mining and machine learning techniques for system design space exploration and automatized optimization2017 International Conference on Applied System Innovation (ICASI)10.1109/ICASI.2017.7988179(1079-1082)Online publication date: May-2017

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MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems
October 2016
463 pages
ISBN:9781450343053
DOI:10.1145/2989081
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 October 2016

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Author Tags

  1. cache references and evictions
  2. caches
  3. memory hierarchy
  4. modeling

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View all
  • (2018)A performance study of the time-varying cache behaviorThe Journal of Supercomputing10.1007/s11227-017-2144-174:2(665-695)Online publication date: 1-Feb-2018
  • (2017)Using data mining and machine learning techniques for system design space exploration and automatized optimization2017 International Conference on Applied System Innovation (ICASI)10.1109/ICASI.2017.7988179(1079-1082)Online publication date: May-2017

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