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Neural network transformation under hardware constraints

Published: 01 October 2016 Publication History

Abstract

There are a number of mature ways to train various kinds of ANNs (artificial neural networks), including the BP (back propagation) based algorithm and so on. These training procedures are usually carried out on some GPU-enabled machine(s); 16-/32-bit-width floating point numbers are used as the NN parameters, without any limitation on the maximum fan-in/fan-out of a single neuron or on the type of activation functions. In contrast, for neuromorphic chips [1][2][3], quite a few hardware-specific constraints (the limited fan-in/fan-out of a single neuron, the limited range of synaptic weights, and the hardware types of neurons or activation functions are usually simpler than the software counterparts) do exist, which makes programming such chips difficult.

References

[1]
P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, etc., A million spiking-neuron integrated circuit with a scalable communication network and interface, Science, vol. 345, no. 6197, pp. 668--673, 2014.
[2]
B. V. Benjamin, P. Gao, E. McQuinn, etc., Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations, Proceedings of the IEEE, vol. 102, pp. 699--716, May 2014.
[3]
S. B. Furber, D. R. Lester, L. A. Plana, etc., Overview of the spinnaker system architecture, IEEE Transactions on Computers, vol. 62, pp. 2454--2467, Dec 2013.
[4]
Steven K. Esser, Paul A. Merolla, John V. Arthur, etc. Convolutional Networks for Fast, Energy-Efficient Neuromorphic Computing. arXiv:1603.08270.
[5]
L. Shi, J. Pei, N. Deng, etc., Development of a neuromorphic computing system, in 2015 IEEE International Electron Devices Meeting (IEDM), pp. 4.3.1--4.3.4, Dec 2015.
[6]
P. Chi, S. Li, C. Xu, etc., Processing-in-memory in reram-based main memory, in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), 2016.

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  • (2019)A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00043(193-196)Online publication date: Jul-2019

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CASES '16: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems
October 2016
187 pages
ISBN:9781450344821
DOI:10.1145/2968455
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Association for Computing Machinery

New York, NY, United States

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Published: 01 October 2016

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ESWEEK'16
ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK
October 1 - 7, 2016
Pennsylvania, Pittsburgh

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  • (2019)A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2019.00043(193-196)Online publication date: Jul-2019

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