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Data speculation support for a chip multiprocessor

Authors:

Lance Hammond,

Mark Willey,

Kunle OlukotunAuthors Info & Claims

ASPLOS VIII: Proceedings of the eighth international conference on Architectural support for programming languages and operating systems

Pages 58 - 69

https://doi.org/10.1145/291069.291020

Published: 01 October 1998 Publication History

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Abstract

Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the support for threadlevel speculation on the Hydra chip multiprocessor (CMP). The support consists of a number of software speculation control handlers and modifications to the shared secondary cache memory system of the CMP This support is evaluated using five representative integer applications. Our results show that the speculative support is only able to improve performance when there is a substantial amount of medium--grained loop-level parallelism in the application. When the granularity of parallelism is too small or there is little inherent parallelism in the application, the overhead of the software handlers overwhelms any potential performance benefits from speculative-thread parallelism. Overall, thread-level speculation still appears to be a promising approach for expanding the class of applications that can be automatically parallelized, but more hardware intensive implementations for managing speculation control are required to achieve performance improvements on a wide class of integer applications.

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Data speculation support for a chip multiprocessor

Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the support for threadlevel speculation on the Hydra chip multiprocessor (CMP). ...
Data speculation support for a chip multiprocessor

Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the support for threadlevel speculation on the Hydra chip multiprocessor (CMP). ...
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency

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Published In

ASPLOS VIII: Proceedings of the eighth international conference on Architectural support for programming languages and operating systems

October 1998

326 pages

ISBN:1581131070

DOI:10.1145/291069

Chairmen:
Dileep Bhandarkar
Intel
,
Anant Agarwal
Massachusetts Institute of Technology, Cambridge

ACM SIGPLAN Notices Volume 33, Issue 11
Nov. 1998
309 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/291006
Chairmen:
Dileep Bhandarkar
Intel
,
Anant Agarwel
Massachusetts Institute of Technology, Cambridge
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 32, Issue 5
Dec. 1998
309 pages
ISSN:0163-5980
DOI:10.1145/384265
Editor:
William M. Waite
Univ. of Colorado, Boulder
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 October 1998

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ASPLOS98

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ASPLOS98: Architectural Support for Programming Languages and Operating Systems

October 2 - 7, 1998

California, San Jose, USA

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ASPLOS VIII Paper Acceptance Rate 28 of 123 submissions, 23%;

Overall Acceptance Rate 535 of 2,713 submissions, 20%

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Cited By

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Ying VJeffrey MSanchez DMartínez JDuato JEeckhout L(2020)T4Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00024(159-172)Online publication date: 30-May-2020
https://dl.acm.org/doi/10.1109/ISCA45697.2020.00024
Boroumand AGhose SPatel MHassan HLucia BAusavarungnirun RHsieh KHajinazar NMalladi KZheng HMutlu OManne SHunter HAltman E(2019)CoNDAProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322266(629-642)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322266
KAWAKAMI SONO TOHTSUKA TINOUE K(2018)Parallel Precomputation with Input Value Prediction for Model Predictive Control SystemsIEICE Transactions on Information and Systems10.1587/transinf.2018PAP0003E101.D:12(2864-2877)Online publication date: 1-Dec-2018
https://doi.org/10.1587/transinf.2018PAP0003
Jeffrey MYing VSubramanian SLee HEmer JSanchez DOskin MInoue K(2018)Harmonizing speculative and non-speculative execution in architectures for ordered parallelismProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00026(217-230)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00026
Subramanian SJeffrey MAbeydeera MLee HYing VEmer JSanchez D(2017)FractalACM SIGARCH Computer Architecture News10.1145/3140659.308021845:2(587-599)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080218
Subramanian SJeffrey MAbeydeera MLee HYing VEmer JSanchez D(2017)FractalProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080218(587-599)Online publication date: 24-Jun-2017
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Abeydeera MSubramanian SJeffrey MEmer JSanchez D(2017)SAM: Optimizing Multithreaded Cores for Speculative Parallelism2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT.2017.37(64-78)Online publication date: Sep-2017
https://doi.org/10.1109/PACT.2017.37
Zhang GChiu VSanchez DHsu WYang CLipasti MLee H(2016)Exploiting semantic commutativity in hardware speculationThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195679(1-12)Online publication date: 15-Oct-2016
https://dl.acm.org/doi/10.5555/3195638.3195679
Jeffrey MSubramanian SAbeydeera MEmer JSanchez DHsu WYang CLipasti MLee H(2016)Data-centric execution of speculative parallel programsThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195644(1-13)Online publication date: 15-Oct-2016
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Estebanez ALlanos DGonzalez-Escribano A(2016)A Survey on Thread-Level Speculation TechniquesACM Computing Surveys10.1145/293836949:2(1-39)Online publication date: 30-Jun-2016
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Data speculation support for a chip multiprocessor

Data speculation support for a chip multiprocessor

Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency