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Memory access buffering in multiprocessors

Authors:

Michel Dubois,

Christoph Scheurich,

Faye BriggsAuthors Info & Claims

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

Pages 320 - 328

https://doi.org/10.1145/285930.285991

Published: 01 August 1998 Publication History

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Cited By

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Nagarajan VSorin DHill MWood DNagarajan VSorin DHill MWood D(2022)Relaxed Memory ConsistencyA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01764-3_5(55-89)Online publication date: 28-Mar-2022
https://doi.org/10.1007/978-3-031-01764-3_5
Nagarajan VSorin DHill MWood D(2020)A Primer on Memory Consistency and Cache Coherence, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00962ED2V01Y201910CAC04915:1(1-294)Online publication date: 4-Feb-2020
https://doi.org/10.2200/S00962ED2V01Y201910CAC049
Lustig DPellauer MMartonosi M(2015)Verifying Correct Microarchitectural Enforcement of Memory Consistency ModelsIEEE Micro10.1109/MM.2015.4735:3(72-82)Online publication date: May-2015
https://doi.org/10.1109/MM.2015.47
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Memory access buffering in multiprocessors

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Published In

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

August 1998

546 pages

ISBN:1581130589

DOI:10.1145/285930

Editor:
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1998

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ISCA98

Sponsor:

SIGARCH
IEEE-CS\TCCA

ISCA98: International Symposium on Computer Architecture

June 27 - July 2, 1998

Barcelona, Spain

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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ISCA '25

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The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

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Cited By

View all

Nagarajan VSorin DHill MWood DNagarajan VSorin DHill MWood D(2022)Relaxed Memory ConsistencyA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01764-3_5(55-89)Online publication date: 28-Mar-2022
https://doi.org/10.1007/978-3-031-01764-3_5
Nagarajan VSorin DHill MWood D(2020)A Primer on Memory Consistency and Cache Coherence, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00962ED2V01Y201910CAC04915:1(1-294)Online publication date: 4-Feb-2020
https://doi.org/10.2200/S00962ED2V01Y201910CAC049
Lustig DPellauer MMartonosi M(2015)Verifying Correct Microarchitectural Enforcement of Memory Consistency ModelsIEEE Micro10.1109/MM.2015.4735:3(72-82)Online publication date: May-2015
https://doi.org/10.1109/MM.2015.47
Chihoub HIbrahim SAntoniu GPerez M(2014)Consistency Management in Cloud Storage SystemsLarge Scale and Big Data10.1201/b17112-11(325-356)Online publication date: 12-Jun-2014
https://doi.org/10.1201/b17112-11
Blanchet GDupouy B(2013)BibliographyComputer Architecture10.1002/9781118577431.biblio(351-356)Online publication date: 20-Feb-2013
https://doi.org/10.1002/9781118577431.biblio
Orozco DGarcia EKhan RLivingston KGao G(2012)Toward high-throughput algorithms on many-core architecturesACM Transactions on Architecture and Code Optimization10.1145/2086696.20867288:4(1-21)Online publication date: 26-Jan-2012
https://dl.acm.org/doi/10.1145/2086696.2086728
Naeem AJantsch ALu Z(2012)Architecture Support and Comparison of Three Memory Consistency Models in NoC Based SystemsProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.27(304-311)Online publication date: 5-Sep-2012
https://dl.acm.org/doi/10.1109/DSD.2012.27
Shankar AShankar A(2012)Distributed Shared Memory ServiceDistributed Programming10.1007/978-1-4614-4881-5_17(299-303)Online publication date: 4-Aug-2012
https://doi.org/10.1007/978-1-4614-4881-5_17
(2011)BibliographyDesigning Network On-Chip Architectures in the Nanoscale Era10.1201/b10477-18(443-475)Online publication date: 9-Feb-2011
https://doi.org/10.1201/b10477-18
Bellens PPerez JBadia RLabarta J(2011)A Study of Speculative Distributed Scheduling on the Cell/B.E.Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium10.1109/IPDPS.2011.23(140-151)Online publication date: 16-May-2011
https://dl.acm.org/doi/10.1109/IPDPS.2011.23
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Memory access buffering in multiprocessors

Memory access buffering in multiprocessors

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