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10.1145/2830772.2830795acmconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
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Avoiding information leakage in the memory controller with fixed service policies

Published: 05 December 2015 Publication History

Abstract

Trusted applications frequently execute in tandem with untrusted applications on personal devices and in cloud environments. Since these co-scheduled applications share hardware resources, the latencies encountered by the untrusted application betray information about whether the trusted applications are accessing shared resources or not. Prior studies have shown that such information leaks can be used by the untrusted application to decipher keys or launch covert-channel attacks. Prior work has also proposed techniques to eliminate information leakage in various shared resources. The best known solution to eliminate information leakage in the memory system incurs high performance penalties. This work develops a comprehensive approach to eliminate timing channels in the memory controller that has two key elements: (i) We shape the memory access behavior of each thread so that it has an unchanging memory access pattern. (ii) We show how efficient memory access pipelines can be constructed to process the resulting memory accesses without introducing any resource conflicts. We mathematically show that the proposed system yields zero information leakage. We then show that various page mapping policies can impact the throughput of our secure memory system. We also introduce techniques to re-order requests from different threads to boost performance without leaking information. Our best solution offers throughput that is 27% lower than that of an optimized non-secure baseline, and that is 69% higher than the best known competing scheme.

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  • (2023)Hardware Support for Constant-Time ProgrammingProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623796(856-870)Online publication date: 28-Oct-2023
  • (2023)Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense SchemesProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589073(1-16)Online publication date: 17-Jun-2023
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cover image ACM Conferences
MICRO-48: Proceedings of the 48th International Symposium on Microarchitecture
December 2015
787 pages
ISBN:9781450340342
DOI:10.1145/2830772
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 December 2015

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  1. hardware security

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  • Intel

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MICRO-48 Paper Acceptance Rate 61 of 283 submissions, 22%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

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  • (2024)Veiled Pathways: Investigating Covert and Side Channels Within GPU Uncore2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00088(1169-1183)Online publication date: 2-Nov-2024
  • (2023)Hardware Support for Constant-Time ProgrammingProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623796(856-870)Online publication date: 28-Oct-2023
  • (2023)Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense SchemesProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589073(1-16)Online publication date: 17-Jun-2023
  • (2022)DAGguise: mitigating memory timing side channelsProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507747(329-343)Online publication date: 28-Feb-2022
  • (2022)Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED)10.1109/SEED55351.2022.00024(190-201)Online publication date: Sep-2022
  • (2022)MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00024(97-104)Online publication date: Oct-2022
  • (2021)Leaky buddiesProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00080(972-984)Online publication date: 14-Jun-2021
  • (2020)When oblivious is notProceedings of the 14th USENIX Conference on Offensive Technologies10.5555/3488877.3488880(3-3)Online publication date: 11-Aug-2020
  • (2019)Innovations in the Memory SystemSynthesis Lectures on Computer Architecture10.2200/S00933ED1V01Y201906CAC04814:2(1-151)Online publication date: 10-Sep-2019
  • (2019)CycloneProceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3352460.3358273(57-72)Online publication date: 12-Oct-2019
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