We have been proposed a low power SRAM using an effective method called “ABC-MT-CMOS” [1]. It controls the backgates to reduce the leakage current when the SRAM is not activated (sleep mode) while retaining the data stored in the memory cells. We also adopted a “CSB Scheme” which clamps both the source lines of the memory cell array and the bit lines. We designed and fabricated test chips containing a 32K-bit gate array SRAM. The experimental results show that the leakage current is reduced to 1/1000 in sleep mode. The active power is 0.27 mW/MHz at 1 V, which is a reduction of 1/12 of a conventional SRAM with a 3.3 V.

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ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

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Published: 10 August 1998

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ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Yoshida HShiotsu YKitagata DYamamoto SSugahara S(2021)Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-SwitchesIEEE Open Journal of Circuits and Systems10.1109/OJCAS.2021.31049452(520-533)Online publication date: 2021
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Yazdani RArnau JGonzalez A(2019)A Low-Power, High-Performance Speech Recognition AcceleratorIEEE Transactions on Computers10.1109/TC.2019.293707568:12(1817-1831)Online publication date: 1-Dec-2019
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https://doi.org/10.1109/WSCAD.2018.00047
M. Sokulski RD. Carreno EZ. Alves M(2018)Evaluating Dead Line Predictors Efficiency with Drowsy Technique2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2018.00046(250-255)Online publication date: Nov-2018
https://doi.org/10.1109/SBESC.2018.00046
Duari CBirla S(2018)Leakage Power Improvement in SRAM Cell with Clamping Diode Using Reverse Body Bias TechniqueProceedings of the 2nd International Conference on Data Engineering and Communication Technology10.1007/978-981-13-1610-4_29(279-287)Online publication date: 4-Oct-2018
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Tripathi TChauhan DSingh D(2016)Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM DesignInternational Journal of Electrical and Electronics Research10.37391/IJEER.0904014:4(110-117)Online publication date: 30-Dec-2016
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Neelima KBharathi M(2015)Gated-VDD Based Single Ended SRAM Arraysi-manager's Journal on Circuits and Systems10.26634/jcir.3.2.34113:2(19-25)Online publication date: 15-May-2015
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