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Performance characterization of a Quad Pentium Pro SMP using OLTP workloads

Authors:

Kimberly Keeton,

David A. Patterson,

Roger C. Raphael,

Walter E. BakerAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 26, Issue 3

Pages 15 - 26

https://doi.org/10.1145/279361.279364

Published: 16 April 1998 Publication History

Abstract

Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these differences is that computers optimized for technical workloads may not provide good performance for commercial applications, and these applications may not fully exploit advances in processor design. To evaluate these issues, we use hardware counters to measure architectural features of a four-processor Pentium Pro-based server running a TPC-C-like workload on an Informix database. We examine the effectiveness of out-of-order execution, branch prediction, speculative execution, superscalar issue and retire, caching and multiprocessor scaling. We find that out-of-order execution, superscalar issue and retire, and branch prediction are not as effective for database workloads as they are for technical workloads, such as SPEC. We find that caches are effective at reducing processor traffic to memory; even larger caches would be helpful to satisfy more data requests. Multiprocessor scaling of this workload is good, but even modest bus utilization degrades application memory latency, limiting database throughput.

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Cited By

Kumar RGrot B(2022)Shooting Down the Server Front-End BottleneckACM Transactions on Computer Systems10.1145/348449238:3-4(1-30)Online publication date: 4-Jan-2022
https://dl.acm.org/doi/10.1145/3484492
Sirin UTözün PPorobic DYasin AAilamaki A(2021)Micro-architectural analysis of in-memory OLTP: RevisitedThe VLDB Journal10.1007/s00778-021-00663-8Online publication date: 31-Mar-2021
https://doi.org/10.1007/s00778-021-00663-8
Falsafi B(2021)Post‐Moore Datacenter Server ArchitectureMulti‐Processor System‐on‐Chip 210.1002/9781119818410.ch6(123-134)Online publication date: 28-Apr-2021
https://doi.org/10.1002/9781119818410.ch6
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Index Terms

Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
1. General and reference
  1. Cross-computing tools and techniques
    1. Measurement
    2. Metrics
2. Hardware
  1. Hardware validation

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 26, Issue 3

Special Issue: Proceedings of the 25th annual international symposium on Computer architecture (ISCA '98)

June 1998

379 pages

ISSN:0163-5964

DOI:10.1145/279361

Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya, Barcelona, Spain
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Issue’s Table of Contents

ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture
April 1998
402 pages
ISBN:0818684917
Chairmen:
Mateo Valero
Univ. Politecnica de Catalunya
,
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison
,
Editor:
Doug DeGroot

Copyright © 1998 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 April 1998

Published in SIGARCH Volume 26, Issue 3

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Cited By

Kumar RGrot B(2022)Shooting Down the Server Front-End BottleneckACM Transactions on Computer Systems10.1145/348449238:3-4(1-30)Online publication date: 4-Jan-2022
https://dl.acm.org/doi/10.1145/3484492
Sirin UTözün PPorobic DYasin AAilamaki A(2021)Micro-architectural analysis of in-memory OLTP: RevisitedThe VLDB Journal10.1007/s00778-021-00663-8Online publication date: 31-Mar-2021
https://doi.org/10.1007/s00778-021-00663-8
Falsafi B(2021)Post‐Moore Datacenter Server ArchitectureMulti‐Processor System‐on‐Chip 210.1002/9781119818410.ch6(123-134)Online publication date: 28-Apr-2021
https://doi.org/10.1002/9781119818410.ch6
XI FMISHIMA TYOKOTA H(2015)Cache-Conscious Data Access for DBMS in Multicore EnvironmentsIEICE Transactions on Information and Systems10.1587/transinf.2014DAP0004E98.D:5(1001-1012)Online publication date: 2015
https://doi.org/10.1587/transinf.2014DAP0004
Zeuch SFreytag J(2015)Selection on Modern CPUsProceedings of the 3rd VLDB Workshop on In-Memory Data Mangement and Analytics10.1145/2803140.2803145(1-8)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2803140.2803145
Simion BRay SBrown ACruz IKnoblock CKröger PTanin EWidmayer P(2012)Surveying the landscapeProceedings of the 20th International Conference on Advances in Geographic Information Systems10.1145/2424321.2424369(376-385)Online publication date: 6-Nov-2012
https://dl.acm.org/doi/10.1145/2424321.2424369
Demme JSethumadhavan S(2011)Rapid identification of architectural bottlenecks via precise event countingACM SIGARCH Computer Architecture News10.1145/2024723.200010739:3(353-364)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/2024723.2000107
Demme JSethumadhavan SIyer RYang QGonzález A(2011)Rapid identification of architectural bottlenecks via precise event countingProceedings of the 38th annual international symposium on Computer architecture10.1145/2000064.2000107(353-364)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/2000064.2000107
Duggan JCetintemel UPapaemmanouil OUpfal ESellis TMiller RKementsietsidis AVelegrakis Y(2011)Performance prediction for concurrent database workloadsProceedings of the 2011 ACM SIGMOD International Conference on Management of data10.1145/1989323.1989359(337-348)Online publication date: 12-Jun-2011
https://dl.acm.org/doi/10.1145/1989323.1989359
Eeckhout L(2010)Computer Architecture Performance Evaluation MethodsSynthesis Lectures on Computer Architecture10.2200/S00273ED1V01Y201006CAC0105:1(1-145)Online publication date: 22-Dec-2010
https://doi.org/10.2200/S00273ED1V01Y201006CAC010
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