System chip test challenges, are there solutions today? (panel)

To meet the challenges involved in designing systems on silicon, IC designers are increasingly adopting a design re-use methodology, in which pre-designed logic modules, often called virtual components (VC) or intellectual property (IP) cores, are integrated together to construct system chips. Testing such increasingly complex systems comprising components that may be “black-boxes” is a major problem. The panel will discuss the challenges associated with testing system chips containing a diverse range of pre-designed VCs and will address the question of whether there are viable solutions today. It will discuss the impact of design re-use on test methodologies and will discuss whether the time to market gains offered by design re-use will be realized without test re-use. It will examine the role of scan, BIST, at-speed testing etc. as virtual component test techniques, and will discuss the issues involved in providing test access to facilitate test re-use. It will debate the impact of the SIA road-map on test requirements and will discuss the limitations in ATE that will have to be overcome and the issues in performance testing that will have to be addressed to test tomorrow's system chips. In addition, it will look at the role of standards (such as those being proposed by VSIA and IEEE) and discuss whether standardization is possible.