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M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture

Authors:

Minho Lee,

Dong Hyun Kang,

Junghoon Kim,

Young Ik EomAuthors Info & Claims

SAC '15: Proceedings of the 30th Annual ACM Symposium on Applied Computing

Pages 2001 - 2006

https://doi.org/10.1145/2695664.2695675

Published: 13 April 2015 Publication History

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Abstract

Phase Change Memory (PCM) has drawn great attention as a main memory due to its attractive characteristics such as non-volatility, byte-addressability, and in-place update. However, since the capacity of PCM is not fully mature yet, hybrid memory architecture that consists of DRAM and PCM has been suggested. In addition, page replacement algorithm based on hybrid memory architecture is actively being studied because existing page replacement algorithms cannot be used on hybrid memory architecture in that they do not consider the two weaknesses of PCM: high write latency and low endurance. In this paper, to mitigate the above hardware limitations of PCM, we revisit the page cache layer for the hybrid memory architecture. We also propose a novel page replacement algorithm, called M-CLOCK, to improve the performance of hybrid memory architecture and the lifespan of PCM. In particular, M-CLOCK aims to reduce the number of PCM writes that negatively affect the performance of hybrid memory architecture. Experimental results clearly show that M-CLOCK outperforms the state-of-the-art page replacement algorithms in terms of the number of PCM writes and effective memory access time by up to 98% and 34%, respectively.

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Wang TWu CTsao CChang YKuo TLiu X(2022)Rethinking the Interactivity of OS and Device Layers in Memory ManagementACM Transactions on Embedded Computing Systems10.1145/353087621:4(1-21)Online publication date: 23-Aug-2022
https://dl.acm.org/doi/10.1145/3530876
Choi JKim KKwak J(2021)TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded SystemsElectronics10.3390/electronics1009111110:9(1111)Online publication date: 8-May-2021
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Salkhordeh RMutlu OAsadi H(2019)An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main MemoriesIEEE Transactions on Computers10.1109/TC.2019.290659768:8(1114-1130)Online publication date: 1-Aug-2019
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M-CLOCK: migration-optimized page replacement algorithm for hybrid DRAM and PCM memory architecture

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Information & Contributors

Information

Published In

SAC '15: Proceedings of the 30th Annual ACM Symposium on Applied Computing

April 2015

2418 pages

ISBN:9781450331968

DOI:10.1145/2695664

Conference Chairs:
Roger L. Wainwright
University of Tulsa
,
Juan Manuel Corchado
University of Salamanca, Spain
,
Program Chairs:
Alessio Bechini
University of Pisa, Italy
,
Jiman Hong
Soongsil University, South Korea

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 April 2015

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Ministry of Science, ICT & Future Planning

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SAC 2015

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SIGAPP

SAC 2015: Symposium on Applied Computing

April 13 - 17, 2015

Salamanca, Spain

Acceptance Rates

SAC '15 Paper Acceptance Rate 291 of 1,211 submissions, 24%;

Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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SAC '25

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The 40th ACM/SIGAPP Symposium on Applied Computing

March 31 - April 4, 2025

Catania , Italy

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Cited By

View all

Wang TWu CTsao CChang YKuo TLiu X(2022)Rethinking the Interactivity of OS and Device Layers in Memory ManagementACM Transactions on Embedded Computing Systems10.1145/353087621:4(1-21)Online publication date: 23-Aug-2022
https://dl.acm.org/doi/10.1145/3530876
Choi JKim KKwak J(2021)TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded SystemsElectronics10.3390/electronics1009111110:9(1111)Online publication date: 8-May-2021
https://doi.org/10.3390/electronics10091111
Salkhordeh RMutlu OAsadi H(2019)An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main MemoriesIEEE Transactions on Computers10.1109/TC.2019.290659768:8(1114-1130)Online publication date: 1-Aug-2019
https://dl.acm.org/doi/10.1109/TC.2019.2906597
Niu NFu FYang BYuan JLai FWang J(2019)WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing ApplicationsIEEE Access10.1109/ACCESS.2019.29048037(35941-35951)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2904803
Puglia GZorzo ADe Rose CPerez TMilojicic D(2019)Non-Volatile Memory File Systems: A SurveyIEEE Access10.1109/ACCESS.2019.28994637(25836-25871)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2899463
Wang LChen XLi X(2018)Data Scheduling Based on Data Label in Hybrid Storage Architecture2018 IEEE 15th International Conference on Mobile Ad Hoc and Sensor Systems (MASS)10.1109/MASS.2018.00083(537-542)Online publication date: Oct-2018
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Jung BLee J(2018)Temporal Locality with a Long Interval: Hybrid Memory System for High-Performance and Low-PowerSoftware Engineering Research, Management and Applications10.1007/978-3-319-98881-8_1(1-15)Online publication date: 12-Oct-2018
https://doi.org/10.1007/978-3-319-98881-8_1
Liu DLin YHuang PZhu XLiang L(2017)Durable and Energy Efficient In-Memory Frequent-Pattern MiningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.268107736:12(2003-2016)Online publication date: Dec-2017
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Chen XSha EJiang WYang CWu TZhuge Q(2017)Refinery swapFuture Generation Computer Systems10.1016/j.future.2017.06.01277:C(52-64)Online publication date: 1-Dec-2017
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Chen XSha EJiang WZhuge QChen JQin JZeng Y(2016)The design of an efficient swap mechanism for hybrid DRAM-NVM systemsProceedings of the 13th International Conference on Embedded Software10.1145/2968478.2968497(1-10)Online publication date: 1-Oct-2016
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