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Mechanistic Modeling of Architectural Vulnerability Factor

Published: 20 January 2015 Publication History

Abstract

Reliability to soft errors is a significant design challenge in modern microprocessors owing to an exponential increase in the number of transistors on chip and the reduction in operating voltages with each process generation. Architectural Vulnerability Factor (AVF) modeling using microarchitectural simulators enables architects to make informed performance, power, and reliability tradeoffs. However, such simulators are time-consuming and do not reveal the microarchitectural mechanisms that influence AVF. In this article, we present an accurate first-order mechanistic analytical model to compute AVF, developed using the first principles of an out-of-order superscalar execution. This model provides insight into the fundamental interactions between the workload and microarchitecture that together influence AVF. We use the model to perform design space exploration, parametric sweeps, and workload characterization for AVF.

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Cited By

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  • (2019)Language Support for Navigating Architecture Design in Closed FormACM Journal on Emerging Technologies in Computing Systems10.1145/336004716:1(1-28)Online publication date: 25-Oct-2019
  • (2019)Ensemble learning based Architecture Vulnerability Factor calculation using partial feature set in processorsJournal of Physics: Conference Series10.1088/1742-6596/1195/1/0120201195(012020)Online publication date: 29-May-2019
  • (2018)CharmProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00023(152-165)Online publication date: 2-Jun-2018
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    Published In

    cover image ACM Transactions on Computer Systems
    ACM Transactions on Computer Systems  Volume 32, Issue 4
    January 2015
    124 pages
    ISSN:0734-2071
    EISSN:1557-7333
    DOI:10.1145/2723895
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 20 January 2015
    Accepted: 01 September 2014
    Revised: 01 June 2014
    Received: 01 September 2013
    Published in TOCS Volume 32, Issue 4

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    Author Tags

    1. Architectural Vulnerability Factor
    2. Computer architecture
    3. analytical modeling
    4. availability
    5. mechanistic modeling
    6. reliability
    7. servicability (RAS)
    8. soft errors

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    • Refereed

    Funding Sources

    • European Research Council under the European Community's Seventh Framework Programme (FP7/2007-2013)/ERC
    • European Community's Seventh Framework Programme (FP7/2007-2013)/ERC
    • Scientific Research - Flanders (FWO)
    • AMD
    • NSF

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    Cited By

    View all
    • (2019)Language Support for Navigating Architecture Design in Closed FormACM Journal on Emerging Technologies in Computing Systems10.1145/336004716:1(1-28)Online publication date: 25-Oct-2019
    • (2019)Ensemble learning based Architecture Vulnerability Factor calculation using partial feature set in processorsJournal of Physics: Conference Series10.1088/1742-6596/1195/1/0120201195(012020)Online publication date: 29-May-2019
    • (2018)CharmProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00023(152-165)Online publication date: 2-Jun-2018
    • (2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016

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