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Dynamic speculation and synchronization of data dependences

Authors:

Andreas Moshovos,

Scott E. Breach,

T. N. Vijaykumar,

Gurindar S. SohiAuthors Info & Claims

ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture

Pages 181 - 193

https://doi.org/10.1145/264107.264189

Published: 01 May 1997 Publication History

Abstract

Data dependence speculation is used in instruction-level parallel (ILP) processors to allow early execution of an instruction before a logically preceding instruction on which it may be data dependent. If the instruction is independent, data dependence speculation succeeds; if not, it fails, and the two instructions must be synchronized. The modern dynamically scheduled processors that use data dependence speculation do so blindly (i.e., every load instruction with unresolved dependences is speculated). In this paper, we demonstrate that as dynamic instruction windows get larger, significant performance benefits can result when intelligent decisions about data dependence speculation are made. We propose dynamic data dependence speculation techniques: (i) to predict if the execution of an instruction is likely to result in a data dependence mis-specalation, and (ii) to provide the synchronization needed to avoid a mis-speculation. Experimental results evaluating the effectiveness of the proposed techniques are presented within the context of a Multiscalar processor.

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Information

Published In

cover image ACM Conferences

ISCA '97: Proceedings of the 24th annual international symposium on Computer architecture

June 1997

350 pages

ISBN:0897919017

DOI:10.1145/264107

Chairmen:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan

ACM SIGARCH Computer Architecture News Volume 25, Issue 2
Special Issue: Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97)
May 1997
349 pages
ISSN:0163-5964
DOI:10.1145/384286
Editors:
Andrew R. Pleszkun
Univ. of Colorado-Boulder, CO
,
Trevor Mudge
Univ. of Michigan
Issue’s Table of Contents

Copyright © 1997 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1997

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ISCA97: International Conference on Computer Architecture

June 1 - 4, 1997

Colorado, Denver, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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https://doi.org/10.1109/ISCA59077.2024.00017
Pu ZZhang GZhang TZhang CZhang YZhao X(2024)ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Access2024 IEEE 42nd International Conference on Computer Design (ICCD)10.1109/ICCD63220.2024.00019(52-59)Online publication date: 18-Nov-2024
https://doi.org/10.1109/ICCD63220.2024.00019
Kim SRos A(2024)Effective Context-Sensitive Memory Dependence Prediction2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00045(515-527)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00045
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Jeong IPark SLee CRo W(2020)CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA47549.2020.00039(383-396)Online publication date: Feb-2020
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