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Generation of synthetic sequential benchmark circuits

Published: 09 February 1997 Publication History

Abstract

Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the effectiveness of new architectures and software. Benchmark circuits arc a precious commodity, and often cannot be found at the correct granularity, or in the desired quantity. In previous work, we have defined important physical characteristics of combinational circuits. We presented a tool (CIRC) to extract them, and gaue an algorithm and tool (GEN) which generates random circuits, parameterized by those characteristics or by a realistic set of defaults. Though a promising step, only a small portion of real circuits are fully combinational. In this paper we extend the effort to model sequential circuits. We propose new characteristics and generate circuits which are sequential. This allows for the generation of truly useful benchmark circuits, both at and beyond the sizes of next-generation FPGAs. By comparing the post-lay out properties of the generated circuits with already existing circuits, we demonstrate that the synthetic circuits are much more realistic than random graphs with the same number of nodes, edges and I/Os.

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cover image ACM Conferences
FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
February 1997
174 pages
ISBN:0897918010
DOI:10.1145/258305
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 February 1997

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  • (2011)Progress in autonomous fault recovery of field programmable gate arraysACM Computing Surveys10.1145/1978802.197881043:4(1-30)Online publication date: 18-Oct-2011
  • (2008)Benchmarking in digital circuit design automationWSEAS Transactions on Circuits and Systems10.5555/1482050.14820657:4(287-310)Online publication date: 1-Apr-2008
  • (2008)Benchmarking in digital circuit designProceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics10.5555/1415563.1415577(58-66)Online publication date: 27-May-2008
  • (2006)PartGenIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89285519:11(1314-1321)Online publication date: 1-Nov-2006
  • (2006)Generating synthetic benchmark circuits for evaluating CAD toolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.86364119:9(1011-1022)Online publication date: 1-Nov-2006
  • (2006)Characterization and parameterized generation of synthetic combinational benchmark circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72891917:10(985-996)Online publication date: 1-Nov-2006
  • (2005)Extra-dimensional Island-Style FPGAsNew Algorithms, Architectures and Applications for Reconfigurable Computing10.1007/1-4020-3128-9_1(3-13)Online publication date: 2005
  • (2003)Extra-dimensional Island-Style FPGAsField Programmable Logic and Application10.1007/978-3-540-45234-8_40(406-415)Online publication date: 2003
  • (2001)Structural analysis and generation of synthetic digital circuits with memoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9208389:1(223-227)Online publication date: 1-Feb-2001
  • (2000)Tolerating operational faults in cluster-based FPGAsProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329205(187-194)Online publication date: 1-Feb-2000
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