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research-article

Memory encryption: A survey of existing techniques

Published: 01 March 2014 Publication History

Abstract

Memory encryption has yet to be used at the core of operating system designs to provide confidentiality of code and data. As a result, numerous vulnerabilities exist at every level of the software stack. Three general approaches have evolved to rectify this problem. The most popular approach is based on complex hardware enhancements; this allows all encryption and decryption to be conducted within a well-defined trusted boundary. Unfortunately, these designs have not been integrated within commodity processors and have primarily been explored through simulation with very few prototypes. An alternative approach has been to augment existing hardware with operating system enhancements for manipulating keys, providing improved trust. This approach has provided insights into the use of encryption but has involved unacceptable overheads and has not been adopted in commercial operating systems. Finally, specialized industrial devices have evolved, potentially adding coprocessors, to increase security of particular operations in specific operating environments. However, this approach lacks generality and has introduced unexpected vulnerabilities of its own. Recently, memory encryption primitives have been integrated within commodity processors such as the Intel i7, AMD bulldozer, and multiple ARM variants. This opens the door for new operating system designs that provide confidentiality across the entire software stack outside the CPU. To date, little practical experimentation has been conducted, and the improvements in security and associated performance degradation has yet to be quantified. This article surveys the current memory encryption literature from the viewpoint of these central issues.

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Published In

cover image ACM Computing Surveys
ACM Computing Surveys  Volume 46, Issue 4
April 2014
463 pages
ISSN:0360-0300
EISSN:1557-7341
DOI:10.1145/2597757
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 March 2014
Accepted: 01 October 2013
Revised: 01 September 2013
Received: 01 April 2013
Published in CSUR Volume 46, Issue 4

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Author Tags

  1. Secure processors
  2. confidentiality
  3. hardware attacks
  4. memory encryption
  5. protection
  6. software attacks

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  • (2024)Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory ProtectionIEEE Internet of Things Journal10.1109/JIOT.2023.333320311:7(12319-12330)Online publication date: 1-Apr-2024
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