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Protecting bus-based hardware IP by secret sharing

Published: 08 June 2008 Publication History

Abstract

Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation is applicable to a broad category of electronic systems with a primary bus. Such designs include (1) numerous IP offerings for USB, PCI, PCI-E, AMBA and other bus standards typically used in system-on-a-chip designs and computer peripherals, (2) SRAM-based FPGAs that are programmed through an input bus, (3) general-purpose and embedded microprocessors, including soft cores, (4) DSPs, (5) network processors, and (6) game consoles. Our key insight is that such designs can be locked by scrambling the central bus by controlled reversible bit-permutations and substitutions. To securely establish a unique code per chip to control bus scrambling, we employ true random number generators and Diffie-Hellman cryptography during activation.

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    cover image ACM Conferences
    DAC '08: Proceedings of the 45th annual Design Automation Conference
    June 2008
    993 pages
    ISBN:9781605581156
    DOI:10.1145/1391469
    • General Chair:
    • Limor Fix
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 08 June 2008

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    Author Tags

    1. computer crime
    2. cryptography
    3. integrated circuits
    4. manufacturing

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    • (2020)How to Retrieve PUF Response from a Fabricated Chip Securely?2020 21st International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED48828.2020.9137044(21-26)Online publication date: Mar-2020
    • (2019)Physical Attacks and CountermeasuresHardware Security10.1016/B978-0-12-812477-2.00015-0(245-290)Online publication date: 2019
    • (2017)Comparative Analysis of Hardware Obfuscation for IP ProtectionProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060495(363-368)Online publication date: 10-May-2017
    • (2017)Circuit Obfuscation and Oracle-guided AttacksProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060494(357-362)Online publication date: 10-May-2017
    • (2017)Cyclic Obfuscation for Creating SAT-Unresolvable CircuitsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060458(173-178)Online publication date: 10-May-2017
    • (2017)A comprehensive hardware/software infrastructure for IP cores design protection2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280156(263-266)Online publication date: Dec-2017
    • (2017)A New Active IC Metering Technique Based on Locking Scan Cells2017 IEEE 26th Asian Test Symposium (ATS)10.1109/ATS.2017.20(40-45)Online publication date: Nov-2017
    • (2017)Physical Unclonable Functions and Intellectual Property Protection TechniquesFundamentals of IP and SoC Security10.1007/978-3-319-50057-7_8(199-222)Online publication date: 25-Jan-2017
    • (2017)Structural Transformation-Based ObfuscationHardware Protection through Obfuscation10.1007/978-3-319-49019-9_9(221-239)Online publication date: 5-Jan-2017
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