A linear programming formulation for security-aware gate sizing

Differential power analysis (DPA) has been shown to be the dominant type of side-channel attacks that significantly jeopardize the security in integrated circuits. It has been shown that the data, the functional unit operations as well as the internal micro-architectures can be detected through current and power analysis. Subsequently, different CMOS logic styles have been proposed in the literature for performing computations in such a manner that the current and power signatures can be concealed through reduction of the variance in transient power dissipation. In this work, we propose a gate sizing formulation based on traditional static CMOS standard cells that improves the security of the circuits while maintaining low overheads in terms of area, power and delay. The proposed algorithm considers all disjoint paths from primary inputs to the primary outputs, performing gate sizing with the objective of balancing the switched path capacitances among the various paths making it difficult to extract power or current signatures through current or power profiling. Further, we show that the path based security aware gate sizing formulation is NP-complete and propose a greedy approximation algorithm based on linear programming. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks and the experimental results indicate a reduction of the variance of transient dynamic power by about 40% with very low overhead in terms of delay, area and power.