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View all- Napoli EDe Caro DPetra NStrollo A(2020)A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data RateIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.294170367:1(121-134)Online publication date: Jan-2020
- Shravana KVeena D(2017)Review on lossless data compression using X-MatchPRO algorithm2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)10.1109/RTEICT.2017.8256767(1095-1100)Online publication date: May-2017
- Dhawan UDehon A(2015)Area-Efficient Near-Associative Memories on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26294717:4(1-22)Online publication date: 23-Jan-2015
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