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Placement for clock period minimization with multiple wave propagation

Authors:

Donald A. Joy,

Maciej J. CiesielskiAuthors Info & Claims

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

Pages 640 - 643

https://doi.org/10.1145/127601.127742

Published: 01 June 1991 Publication History

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References

[1]

J.P. Fishburn, "Clock Skew Optimization", IEEE Trans On Computers, Vol. 39, No. 7, pp. 945-951, July 1990.

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[2]

D. A. Joy, M. J. Ciesielski, "Clock Period Minimization in Standard Cell Layout", Int. Workshop on Layout Synthesis Proc. 1990, Microelectronics Center of North Carolina, pp.

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[3]

D. A. Joy, M. J. Ciesielski, "Clock Period Minimization with Simultaneous Multiple Signal Propagation", Submitted to IEEE Trans. on Computer-Aided Design.

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[4]

J. White, N. Weiner, D. Webber, K. Kundert, P. Moore, R. A. galeh, A. ganglovanni-Vincentelll, A. R. Newton, "Relax2.3 User's Guide" Dept. of EE and CS, University of California, Berkeley.

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Lam WBrayton RSangiovanni-Vincentelli A(2006)Valid clock frequencies and their computation in wavepipelined circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50394615:7(791-807)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.503946
Jennings GJennings E(2006)A discrete syntax for level-sensitive latched circuits having n clocks and m phasesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48627715:1(111-126)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.486277
Gray CLiu WCavin R(2006)Timing constraints for wave-pipelined systemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.29803513:8(987-1004)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.298035
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Index Terms

Placement for clock period minimization with multiple wave propagation
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Integrated circuits

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Information

Published In

DAC '91: Proceedings of the 28th ACM/IEEE Design Automation Conference

June 1991

783 pages

ISBN:0897913957

DOI:10.1145/127601

Chairman:
A. Richard Newton
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1991

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DAC91: The 28th ACM/IEEE Design Automation Conference

June 17 - 22, 1991

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Lam WBrayton RSangiovanni-Vincentelli A(2006)Valid clock frequencies and their computation in wavepipelined circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50394615:7(791-807)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.503946
Jennings GJennings E(2006)A discrete syntax for level-sensitive latched circuits having n clocks and m phasesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.48627715:1(111-126)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.486277
Gray CLiu WCavin R(2006)Timing constraints for wave-pipelined systemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.29803513:8(987-1004)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.298035
Sakallah KMudge TBurks TDavidson E(2006)Synchronization of pipelinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.23860612:8(1132-1146)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.238606
Joy DCiesielski M(2006)Clock period minimization with wave pipeliningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.22973012:4(461-472)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.229730
Wong DDe Micheli GFlynn M(2006)Designing high-performance digital circuits using wave pipeliningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.18484112:1(25-46)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.184841
Friedman E(2001)Clock distribution networks in synchronous digital integrated circuitsProceedings of the IEEE10.1109/5.92964989:5(665-692)Online publication date: May-2001
https://doi.org/10.1109/5.929649
Friedman E(1999)Clock Distribution In Synchronous SystemsWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7605Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W7605
Burleson WCiesielski MKlass FLiu W(1998)Wave-pipeliningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.7113176:3(464-474)Online publication date: 1-Sep-1998
https://dl.acm.org/doi/10.1109/92.711317
Takahashi AInoue KKajitani YOtten RYasuura H(1997)Clock-tree routing realizing a clock-schedule for semi-synchronous circuitsProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266487(260-265)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266487
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Clock period minimization with wave pipelining

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