Article

Efficient synthesis of speed-independent combinational logic circuits

Authors:

W. B. Toms,

D. A. EdwardsAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1022 - 1026

https://doi.org/10.1145/1120725.1120782

Published: 18 January 2005 Publication History

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Abstract

Speed-Independent synthesis of combinational logic datapath circuits using tools such as Petrify is often inefficient or infeasible because such circuits typically contain many concurrent inputs and independent outputs. This paper presents a practical method for generating arbitrary combinational logic circuits, using a sub-class of speed-independent circuits known as Strongly-Indicating circuits, without the need to verify the speed-independence of the implementation through construction of a state-graph or other method.

References

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R. L. Rudell. "Logic Synthesis for VLSI Design", PhD thesis, University of California at Berkeley, 1989.]]

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C. Seitz. "System Timing", C.A. Mead and L. A. Conway (eds), Introduction to VLSI systems, Addison-Wesley, 1980.]]

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W. B. Toms "Synthesis of QDI Datapaths", PhD thesis, University of Manchester, 2004.]]

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V. I. Varshavsky, ed. "Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems", Kluwer Academic Publishers. 1990.]]

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Balasubramanian PMastorakis N(2021)Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR ImplementationElectronics10.3390/electronics1012142510:12(1425)Online publication date: 14-Jun-2021
https://doi.org/10.3390/electronics10121425
Balasubramanian PMaskell DMastorakis N(2020)Speed, energy and area optimized early output quasi-delay-insensitive array multipliersPLOS ONE10.1371/journal.pone.022834315:2(e0228343)Online publication date: 3-Feb-2020
https://doi.org/10.1371/journal.pone.0228343
Balasubramanian PMaskell DNaayagi RMastorakis N(2019)Early Output Quasi-Delay-Insensitive Array MultipliersElectronics10.3390/electronics80404448:4(444)Online publication date: 18-Apr-2019
https://doi.org/10.3390/electronics8040444
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Information & Contributors

Information

Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2005

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Article

Conference

ASPDAC05

Sponsor:

SIGDA

ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

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Balasubramanian PMastorakis N(2021)Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR ImplementationElectronics10.3390/electronics1012142510:12(1425)Online publication date: 14-Jun-2021
https://doi.org/10.3390/electronics10121425
Balasubramanian PMaskell DMastorakis N(2020)Speed, energy and area optimized early output quasi-delay-insensitive array multipliersPLOS ONE10.1371/journal.pone.022834315:2(e0228343)Online publication date: 3-Feb-2020
https://doi.org/10.1371/journal.pone.0228343
Balasubramanian PMaskell DNaayagi RMastorakis N(2019)Early Output Quasi-Delay-Insensitive Array MultipliersElectronics10.3390/electronics80404448:4(444)Online publication date: 18-Apr-2019
https://doi.org/10.3390/electronics8040444
Balasubramanian PMaskell DMastorakis N(2018)Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry LogicElectronics10.3390/electronics71002437:10(243)Online publication date: 9-Oct-2018
https://doi.org/10.3390/electronics7100243
Balasubramanian P(2016)Comments on "Dual-rail asynchronous logic multi-level implementation"Integration, the VLSI Journal10.1016/j.vlsi.2015.08.00152:C(34-40)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.08.001
Balasubramanian PDhivyaa DJayakirthika JKaviyarasi PPrasad K(2013)Low power self-timed carry lookahead adders2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2013.6674684(457-460)Online publication date: Aug-2013
https://doi.org/10.1109/MWSCAS.2013.6674684
Balasubramanian PEdwards DToms W(2012)Redundant logic insertion and latency reduction in self-timed addersVLSI Design10.1155/2012/5753892012(10-10)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/575389
Balasubramanian PEdwards D(2008)Efficient Realization of Strongly Indicating Function BlocksProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.103(429-432)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.1109/ISVLSI.2008.103

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