Article

Simultaneous floorplanning and buffer block planning

Authors:

Iris Hui-Ru Jiang,

Yao-Wen Chang,

Jing-Yang Jou,

Kai-Yuan ChaoAuthors Info & Claims

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Pages 431 - 434

https://doi.org/10.1145/1119772.1119858

Published: 21 January 2003 Publication History

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Abstract

As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect delay and reduce the number of buffers needed.

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Cited By

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He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
Dong QYang BLi JNakatake SLombardi FBhanja SMassoud YBahar R(2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531636
He XDong SMa YHong X(2009)Simultaneous buffer and interlayer via planning for 3D floorplanningProceedings of the 2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810385(740-745)Online publication date: 16-Mar-2009
https://dl.acm.org/doi/10.1109/ISQED.2009.4810385
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Published In

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

January 2003

865 pages

ISBN:0780376609

DOI:10.1145/1119772

General Chair:
Hiroto Yasuura

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 21 January 2003

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He ODong SBian JGoto S(2011)Buffer planning for IP placement using sliced-LFFVLSI Design10.1155/2011/5308512011(1-10)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1155/2011/530851
Dong QYang BLi JNakatake SLombardi FBhanja SMassoud YBahar R(2009)Incremental buffer insertion and module resizing algorithm using geometric programmingProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531636(413-416)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531636
He XDong SMa YHong X(2009)Simultaneous buffer and interlayer via planning for 3D floorplanningProceedings of the 2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810385(740-745)Online publication date: 16-Mar-2009
https://dl.acm.org/doi/10.1109/ISQED.2009.4810385
He ODong SBian JMa YHong XZhou HMacii EYan ZMassoud Y(2007)An effective buffer planning algorithm for IP based fixed-outline SOC placementProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228917(564-569)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228917
Chang YChen TChen H(2007)Physical Design for System-On-A-ChipEssential Issues in SOC Design10.1007/1-4020-5352-5_9(311-403)Online publication date: 2007
https://doi.org/10.1007/1-4020-5352-5_9
Guo JPapanikolaou AMarchal PCatthoor FHirose F(2006)Physical design implementation of segmented buses to reduce communication energyProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118311(42-47)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118311
Cheng YChang YImai M(2004)Integrating buffer planning with floorplanning for simultaneous multi-objective optimizationProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015260(624-627)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015260
Yi-Hui Cheng Yao-Wen Chang (2004)Integrating buffer planning with floorplanning for simultaneous multi-objective optimizationASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337667(624-627)Online publication date: 2004
https://doi.org/10.1109/ASPDAC.2004.1337667
Lee HChang YHsu JYang HGetreu IFix LLavagno L(2003)Multilevel floorplanning/placement for large-scale modules using B*-treesProceedings of the 40th annual Design Automation Conference10.1145/775832.776037(812-817)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.776037
Hsun-Cheng Lee Yao-Wen Chang Jer-Ming Hsu Yang H(2003)Multilevel floorplanning/placement for large-scale modules using B*-treesProceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)10.1109/DAC.2003.1219130(812-817)Online publication date: 2003
https://doi.org/10.1109/DAC.2003.1219130

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Integrating buffer planning with floorplanning for simultaneous multi-objective optimization

Simultaneous floor plan and buffer-block optimization

Buffer block planning for interconnect-driven floorplanning

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