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Energy-efficient and high-performance instruction fetch using a block-aware ISA

Authors:

Christos KozyrakisAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 36 - 41

https://doi.org/10.1145/1077603.1077614

Published: 08 August 2005 Publication History

Abstract

The front-end in superscalar processors must deliver high application performance in an energy-effective manner. Impediments such as multi-cycle instruction accesses, instruction-cache misses, and mispredictions reduce performance by 48% and increase energy consumption by 21%. This paper presents a block-aware instruction set architecture (BLISS) that defines basic block descriptors in addition to the actual instructions in a program. BLISS allows for a decoupled front-end that reduces the time and energy spent on misspeculated instructions. It also allows for accurate instruction prefetching and energy efficient instruction access. A BLISS-based front-end leads to 14% IPC, 16% total energy, and 83% energy-delay-squared product improvements for wide-issue processors

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Cited By

Mohammadi MAamodt TDally W(2017)CG-OoOACM Transactions on Architecture and Code Optimization10.1145/315103414:4(1-26)Online publication date: 5-Dec-2017
https://dl.acm.org/doi/10.1145/3151034
Wei LJian-qing X(2013)Low-Power Design of Hybrid Instruction Cache Based on Branch Prediction and Drowsy CacheThe Proceedings of the Second International Conference on Communications, Signal Processing, and Systems10.1007/978-3-319-00536-2_40(335-343)Online publication date: 24-Oct-2013
https://doi.org/10.1007/978-3-319-00536-2_40
Zmily AKozyrakis CKim TSainrat PLumetta SNavarro N(2007)A low power front-end for embedded processors using a block-aware instruction setProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289926(267-276)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289881.1289926
Show More Cited By

Index Terms

Energy-efficient and high-performance instruction fetch using a block-aware ISA
1. Computer systems organization
  1. Architectures
    1. Serial architectures

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Published In

cover image ACM Conferences

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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ISLPED05

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Mohammadi MAamodt TDally W(2017)CG-OoOACM Transactions on Architecture and Code Optimization10.1145/315103414:4(1-26)Online publication date: 5-Dec-2017
https://dl.acm.org/doi/10.1145/3151034
Wei LJian-qing X(2013)Low-Power Design of Hybrid Instruction Cache Based on Branch Prediction and Drowsy CacheThe Proceedings of the Second International Conference on Communications, Signal Processing, and Systems10.1007/978-3-319-00536-2_40(335-343)Online publication date: 24-Oct-2013
https://doi.org/10.1007/978-3-319-00536-2_40
Zmily AKozyrakis CKim TSainrat PLumetta SNavarro N(2007)A low power front-end for embedded processors using a block-aware instruction setProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289926(267-276)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289881.1289926
Curtis-Maury MDzierwa JAntonopoulos CNikolopoulos D(2006)Online strategies for high-performance power-aware thread execution on emerging multiprocessorsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898699.1898824(298-298)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898699.1898824
Zmily AKozyrakis CGielen G(2006)Simultaneously improving code size, performance, and energy in embedded processorsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131544(224-229)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131544
Curtis-Maury MDzierwa JAntonopoulos CNikolopoulos D(2006)Online strategies for high-performance power-aware thread execution on emerging multiprocessorsProceedings 20th IEEE International Parallel & Distributed Processing Symposium10.1109/IPDPS.2006.1639598(8 pp.)Online publication date: 2006
https://doi.org/10.1109/IPDPS.2006.1639598

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