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Article

System-wide performance monitors and their application to the optimization of coherent memory accesses

Authors:

Jean-Francois Collard,

Sami YehiaAuthors Info & Claims

PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming

Pages 247 - 254

https://doi.org/10.1145/1065944.1065977

Published: 15 June 2005 Publication History

Abstract

Inspired by recent advances in microprocessor performance monitors, this paper shows how a shared-memory multiprocessor chipset and interconnect can be equipped with performance monitors that associate performance events with the PCs of the individual instructions causing these events. Such monitors greatly simplify performance debugging of shared-memory programs---for example, they make finding pairs of instructions in false sharing straightforward. These monitors also enable precise feedback-directed compiler optimizations and, as a second contribution, we show how they can guide the code generator to use the version of the load instruction that makes the best use of the coherence protocol. Experiments show up to almost 10% coherence traffic reduction on SPLASH2 applications.

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Cited By

Kyung HPark GKwak JJeong WKim TPark SCho YWainwright RHaddad HShin SKoo Y(2007)Performance monitor unit design for an AXI-based multi-core SoC platformProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244336(1565-1572)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1244002.1244336
Kim JHsu WYew P(2007)COBRAProceedings of the 2007 International Conference on Parallel Processing10.1109/ICPP.2007.23Online publication date: 10-Sep-2007
https://dl.acm.org/doi/10.1109/ICPP.2007.23

Index Terms

System-wide performance monitors and their application to the optimization of coherent memory accesses
1. Computer systems organization

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Published In

cover image ACM Conferences

PPoPP '05: Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming

June 2005

310 pages

ISBN:1595930809

DOI:10.1145/1065944

General Chair:
Keshav Pingali
Cornell University
,
Program Chairs:
Katherine Yelick
University of California, Berkeley and LBNL
,
Andrew Grimshaw
University of Virginia

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 June 2005

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PPoPP05

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PPoPP05: ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming 2005

June 15 - 17, 2005

IL, Chicago, USA

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Overall Acceptance Rate 230 of 1,014 submissions, 23%

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Cited By

Kyung HPark GKwak JJeong WKim TPark SCho YWainwright RHaddad HShin SKoo Y(2007)Performance monitor unit design for an AXI-based multi-core SoC platformProceedings of the 2007 ACM symposium on Applied computing10.1145/1244002.1244336(1565-1572)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1244002.1244336
Kim JHsu WYew P(2007)COBRAProceedings of the 2007 International Conference on Parallel Processing10.1109/ICPP.2007.23Online publication date: 10-Sep-2007
https://dl.acm.org/doi/10.1109/ICPP.2007.23

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