More Web Proxy on the site http://driver.im/

Article

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Authors:

Ashish Srivastava,

Dennis Sylvester,

Stephen DirectorAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 535 - 540

https://doi.org/10.1145/1065579.1065718

Published: 13 June 2005 Publication History

Abstract

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

References

[1]

A. Chandrakasan, W.J. Bowhill, and F. Fox, Design of high-performance microprocessor circuits, IEEE Press, 2001.

Digital Library

[2]

T. Karnik, S. Borkar, and V. De, "Sub-90 nm technologies challenges and opportunities for CAD," ACM/IEEE ICCAD, pp. 203--206, 2002.

Digital Library

[3]

X. Bai, et al., "Uncertainty aware circuit optimization," ACM/IEEE DAC, pp.58--63, 2002.

Digital Library

[4]

S. Raj, S. Vrudhula, and J. Wang, "A methodology to improve timing yield in the presence of process variations," ACM/IEEE DAC, pp. 448--453, 2004.

Digital Library

[5]

S. Choi, B. Paul and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," IEEE/ACM DAC, pp. 454--459, 2004.

Digital Library

[6]

A. Srivastava, D. Sylvester, and D. Blaauw, "Statistical optimization of leakage power considering process variations using dual-Vth and sizing," ACM/IEEE DAC, pp. 773--778, 2004.

Digital Library

[7]

H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," ACM/IEEE ICCAD, pp. 621--625, 2003.

Digital Library

[8]

C. Viswesweriah et al, "First-order incremental block-based statistical timing analysis," ACM/IEEE DAC, 2004.

Digital Library

[9]

A. Agarwal et al., "Statistical timing analysis using bounds and selective enumeration," IEEE TCAD, pp. 1243--1260, Sept. 2003.

Digital Library

[10]

S. Bhardwaj, S. Vrudhula, and D. Blaauw, "TAU: Timing analysis under uncertainty," ACM/IEEE ICCAD, pp. 615--620, Nov. 2003.

Digital Library

[11]

A. Devgan and C. Kashyap, "Block-Based statistical timing analysis with uncertainty," ACM/IEEE ICCAD, pp. 607--614, 2003.

Digital Library

[12]

M. Orshansky and A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," ACM/IEEE DAC, pp. 337--342, 2004.

Digital Library

[13]

R.R. Rao, et al., "Statistical analysis of subthreshold leakage current for VLSI circuits," IEEE Trans. VLSI Systems, pp.131--139, Feb. 2004.

Digital Library

[14]

R.R. Rao, et al., "Parametric yield estimation considering leakage variability," ACM/IEEE DAC, pp. 442--447, 2004.

Digital Library

[15]

K. Bowman et al., "Impact of die-to-die and within-die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration", IEEE JSSC, pp.183--190, Feb. 2002.

[16]

S. Duvall, "Statistical Circuit Modeling and Optimization," Workshop on Statistical Metrology, pp.56--63, 2000.

[17]

S. D. Samaan, "The impact of device parameter variation on the frequency and performance of VLSI chips," ACM/IEEE ICCAD, pp. 343--346, 2004.

Digital Library

[18]

A. Papoulis, Probability, Random Variables, and Stochastic Processes, McGraw-Hill Inc, New York, 1991.

[19]

S. Tsukiyama, M. Tanaka, and M. Fukui, "A new statistical static timing analyzer considering correlation between delays," Proc. TAU, pp. 27--33, Dec. 2002.

Digital Library

[20]

C. Clark, "The greatest of a finite set of random variables," Operations Research, vol. 9, pp. 85--91, 1961.

Digital Library

[21]

A. Abu-Dayya and N. Beaulieu, "Outage probabilities in the presence of correlated lognormal interferers," IEEE Trans. Vehicular Technology, pp.164--173, Feb. 1994.

[22]

S.C. Schwartz and Y.S. Yeh, "On the distribution function and moments of power sums with lognormal components," Bell Systems Technical Journal, vol.61, pp.1441--1462, Sep. 1982.

[23]

J. H. Cadwell, "The bivariate normal integral," Biometrika, pp. 31--35, Dec. 1951.

[24]

F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. ISCAS, pp. 695--698, May 1989.

[25]

http://www.cbl.ncsu.edu

Cited By

Xu YTeich J(2016)Hierarchical Statistical Leakage Analysis and Its ApplicationACM Transactions on Design Automation of Electronic Systems10.1145/289682021:4(1-22)Online publication date: 2-Sep-2016
https://dl.acm.org/doi/10.1145/2896820
Abbas ZOlivieri M(2016)Optimal transistor sizing for maximum yield in variation-aware standard cell designInternational Journal of Circuit Theory and Applications10.1002/cta.216744:7(1400-1424)Online publication date: 1-Jul-2016
https://dl.acm.org/doi/10.1002/cta.2167
Fang CYang FZeng XLi X(2014)BMF-BDProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593099(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593099
Show More Cited By

Recommendations

Parametric yield estimation considering leakage variability
DAC '04: Proceedings of the 41st annual Design Automation Conference

Leakage current has become a stringent constraint in modern processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must ...
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance

Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the ...
Gate-length biasing for runtime-leakage control

Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC05

Sponsor:

DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

37
Total Citations
View Citations
523
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 02 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Xu YTeich J(2016)Hierarchical Statistical Leakage Analysis and Its ApplicationACM Transactions on Design Automation of Electronic Systems10.1145/289682021:4(1-22)Online publication date: 2-Sep-2016
https://dl.acm.org/doi/10.1145/2896820
Abbas ZOlivieri M(2016)Optimal transistor sizing for maximum yield in variation-aware standard cell designInternational Journal of Circuit Theory and Applications10.1002/cta.216744:7(1400-1424)Online publication date: 1-Jul-2016
https://dl.acm.org/doi/10.1002/cta.2167
Fang CYang FZeng XLi X(2014)BMF-BDProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593099(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593099
Abbas ZOlivieri MYakupov MRipp A(2013)Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)Microelectronics Journal10.1016/j.mejo.2012.11.00444:4(321-331)Online publication date: Apr-2013
https://doi.org/10.1016/j.mejo.2012.11.004
Xu YLi BHasholzner RRohfleisch BHaubelt CTeich JRosenstiel WMacii E(2012)Variation-aware leakage power model extraction for system-level hierarchical power analysisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492798(346-351)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492798
Palermo GSilvano CZaccaria V(2012)A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific ConstraintsACM Transactions on Embedded Computing Systems10.1145/2220336.222034111:2(1-28)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1145/2220336.2220341
Rogachev AWan LChen DPhillips JHu AGraeb H(2011)Temperature aware statistical static timing analysisProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132353(103-110)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132353
Fang JSapatnekar S(2011)Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliabilityProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950948(689-694)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950948
Wang JGong NHou LPeng XSridhar RWu W(2011)Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P–V–T fluctuationsMicroelectronics Reliability10.1016/j.microrel.2011.06.01151:9-11(1498-1502)Online publication date: Sep-2011
https://doi.org/10.1016/j.microrel.2011.06.011
Kumar AAnis M(2010)FPGA design for timing yield under process variationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201155518:3(423-435)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011555
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten