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Article

Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model

Published: 13 June 2005 Publication History

Abstract

Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing and operational variations become more and more significant. Due to the nonlinearity of the mapping from variation sources to the gate/wire delay, the distribution of the delay is no longer Gaussian even if the variation sources are normally distributed. A novel quadratic timing model is proposed to capture the non-linearity of the dependency of gate/wire delays and arrival times on the variation sources. Systematic methodology is also developed to evaluate the correlation and distribution of the quadratic timing model. Based on these, a novel statistical timing analysis algorithm is propose which retains the complete correlation information during timing analysis and has the same computation complexity as the algorithm based on the canonical timing model. Tested on the ISCAS circuits, the proposed algorithm shows 10x accuracy improvement over the existing first order algorithm while no significant extra runtime is needed.

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Cited By

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  • (2020)VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay ModelsIEEE Access10.1109/ACCESS.2020.30352638(197194-197202)Online publication date: 2020
  • (2020)Exact Distribution of the Max/Min of Two Correlated Random VariablesWireless Personal Communications10.1007/s11277-020-07750-zOnline publication date: 27-Aug-2020
  • (2019)EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281871338:4(705-718)Online publication date: Apr-2019
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    cover image ACM Conferences
    DAC '05: Proceedings of the 42nd annual Design Automation Conference
    June 2005
    984 pages
    ISBN:1595930582
    DOI:10.1145/1065579
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 13 June 2005

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    Cited By

    View all
    • (2020)VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay ModelsIEEE Access10.1109/ACCESS.2020.30352638(197194-197202)Online publication date: 2020
    • (2020)Exact Distribution of the Max/Min of Two Correlated Random VariablesWireless Personal Communications10.1007/s11277-020-07750-zOnline publication date: 27-Aug-2020
    • (2019)EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281871338:4(705-718)Online publication date: Apr-2019
    • (2018)From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer EraIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.11.211(2-15)Online publication date: 2018
    • (2016)Least Squares Approximation to the Distribution of Project Completion Times with Gaussian UncertaintyOperations Research10.1287/opre.2016.152864:6(1406-1421)Online publication date: 1-Dec-2016
    • (2016)Logic depth aware context independent timing model generation10.1063/1.4942704(020022)Online publication date: 2016
    • (2016)Concurrent multi-mode timing model generation for hierarchical timing analysis10.1063/1.4942699(020017)Online publication date: 2016
    • (2016)Challenges in probabilistic timing model generation in integrated circuits10.1063/1.4942690(020008)Online publication date: 2016
    • (2015)A Skew-Normal Canonical Model for Statistical Static Timing AnalysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.2501370(1-10)Online publication date: 2015
    • (2015)Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning ElementsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.243214334:11(1784-1797)Online publication date: Nov-2015
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