Article

An automatic testbench generation tool for a SystemC functional verification methodology

Authors:

Karina R. G. da Silva,

Elmar U. K. Melcher,

Guido Araujo,

Valdiney Alves PimentaAuthors Info & Claims

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

Pages 66 - 70

https://doi.org/10.1145/1016568.1016592

Published: 04 September 2004 Publication History

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Abstract

The advent of new 90nm/130nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this paper we propose an automatic verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint functional verification. Our approach uses the SystemC Verification Library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.

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Cited By

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Mohamed KMohamed K(2024)Pre-Silicon Verification and Post-Silicon Validation MethodologiesHeterogeneous SoC Design and Verification10.1007/978-3-031-56152-8_4(85-131)Online publication date: 23-Mar-2024
https://doi.org/10.1007/978-3-031-56152-8_4
Ismael MHroub AAbu-Issa A(2023)AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification2023 International Conference on Microelectronics (ICM)10.1109/ICM60448.2023.10378885(162-167)Online publication date: 17-Dec-2023
https://doi.org/10.1109/ICM60448.2023.10378885
McEllin JConway RRyan C(2022)AVERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution2022 33rd Irish Signals and Systems Conference (ISSC)10.1109/ISSC55427.2022.9826162(1-8)Online publication date: 9-Jun-2022
https://doi.org/10.1109/ISSC55427.2022.9826162
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Index Terms

An automatic testbench generation tool for a SystemC functional verification methodology
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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Information & Contributors

Information

Published In

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

September 2004

296 pages

ISBN:1581139470

DOI:10.1145/1016568

General Chair:
Edna Natividade da Silva Barros
Federal University of Pernambuco, Brazil
,
Program Chairs:
Flàvio Rech Wagner
Federal University of Rio Grande do Sul, Brazil
,
Luigi Carro
Federal University of Rio Grande do Sul, Brazil
,
Franz Josef Rammig
University of Paderborn, Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 September 2004

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Conference

SBCCI04

Sponsor:

SBCCI04: 17th Symposium on Integrated Circuits and System Design

September 7 - 11, 2004

Pernambuco, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

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Mohamed KMohamed K(2024)Pre-Silicon Verification and Post-Silicon Validation MethodologiesHeterogeneous SoC Design and Verification10.1007/978-3-031-56152-8_4(85-131)Online publication date: 23-Mar-2024
https://doi.org/10.1007/978-3-031-56152-8_4
Ismael MHroub AAbu-Issa A(2023)AUTG: An Automatic UVM-based TestBench Generator for VLSI Chip Design Verification2023 International Conference on Microelectronics (ICM)10.1109/ICM60448.2023.10378885(162-167)Online publication date: 17-Dec-2023
https://doi.org/10.1109/ICM60448.2023.10378885
McEllin JConway RRyan C(2022)AVERT: An Automatic Verilog Testbench Generation Tool for Grammatical Evolution2022 33rd Irish Signals and Systems Conference (ISSC)10.1109/ISSC55427.2022.9826162(1-8)Online publication date: 9-Jun-2022
https://doi.org/10.1109/ISSC55427.2022.9826162
Silva TMorais DAndrade HNunes FKurt Melcher ENogueira Lima ABrito A(2018)A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous Architectures2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2018.8533247(4849-4854)Online publication date: Aug-2018
https://doi.org/10.1109/SBCCI.2018.8533247
Syafalni ISurantha NLam DSutisna NNagao YWakasugi KTongxin YOchi HTsuchiya T(2016)Assertion-based verification of industrial WLAN system2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527407(982-985)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7527407
Haghi HChupilko MKamkin ANavabi Z(2016)ESL design with RTL-verified predesigned abstract communication channels2016 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2016.7807632(1-7)Online publication date: Oct-2016
https://doi.org/10.1109/EWDTS.2016.7807632
Herber PGlesner S(2015)Verification of Embedded Real-time SystemsFormal Modeling and Verification of Cyber-Physical Systems10.1007/978-3-658-09994-7_1(1-25)Online publication date: 6-Jun-2015
https://doi.org/10.1007/978-3-658-09994-7_1
Herber PGlesner S(2013)A HW/SW co-verification framework for SystemCACM Transactions on Embedded Computing Systems10.1145/2435227.243525712:1s(1-23)Online publication date: 29-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435257
Hung STu CLiaw Y(2013)V2X: An automated tool for building SystemC-based simulation environments in designing multicore systems-on-chipsJournal of the Chinese Institute of Engineers10.1080/02533839.2012.72602436:1(48-62)Online publication date: Jan-2013
https://doi.org/10.1080/02533839.2012.726024
Srivastava RGupta GPatankar SMudgil N(2013)Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and ToolVLSI Design and Test10.1007/978-3-642-42024-5_34(284-293)Online publication date: 2013
https://doi.org/10.1007/978-3-642-42024-5_34
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A methodology aimed at better integration of functional verification and RTL design

An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC

Induction-Based Formal Verification of SystemC TLM Designs