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A 5.4 GHz fully-integrated low-noise mixer

Published: 06 September 2010 Publication History

Abstract

A fully integrated CMOS low-noise mixing circuit operating at an RF frequency of 5.4 GHz is presented in this paper. The mixer is a Gilbert cell with a low-noise transconductor stage and a current-bleeding circuit. The transconductor, designed using the power constrained simultaneous noise and input match technique, together with the bleeding circuit enables the mixer to have a measured single-sideband noise figure of 7.8 dB and a power conversion gain of 13.1 dB. The output-referred 1-dB compression point, OP1dB, is -5 dBm and the output-referred IP3 is +6.9 dBm. All of the inductors are on-chip and the size of the mixer core is only 380 um x 350 um (0.133 mm2).

References

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H. Sjoland, A. Karimi-Sanjaani, and A. Abidi, "A merged CMOS LNA and mixer for a WCDMA receiver," IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 1045--1050, June 2003.
[2]
S.-G. Lee and J.-K. Choi, "Current-reuse bleeding mixer," Electronics Letters, vol. 36, no. 8, pp. 696--697, Apr 2000.
[3]
J. Park, C.-H. Lee, B.-S. Kim, and J. Laskar, "Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers," IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4372--4380, Dec. 2006.
[4]
H. Darabi and J. Chiu, "A noise cancellation technique in active RF-CMOS mixers," IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2628--2632, Dec. 2005.
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T.-A. Phan, C.-W. Kim, M.-S. Kang, S.-G. Lee, and C.-D. Su, "A High Performance CMOS Direct Down Conversion Mixer for UWB System," IEICE Transactions on Electronics, vol. E88-C, no. 12, pp. 2316--2321, Dec. 2005.
[6]
F. Skandar, S. Douss, and M. Loulou, "A 3.1--4.8 GHz new CMOS mixer topology for IEEE 802.15.3a UWB standard receivers," 50th Midwest Symposium on Circuits and Systems, pp. 431--434, Aug. 2007.
[7]
S. S. K. Ho and C. E. Saavedra, "A CMOS Broadband Low-Noise Mixer with Noise Cancellation," IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 5, pp. 1126--1132, May 2010.
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T.-K. Nguyen, C.-H. Kim, G.-J. Ihm, M.-S. Yang, and S.-G. Lee, "CMOS low-noise amplifier design optimization techniques," IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 5, pp. 1433--1442, May 2004.
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[10]
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[11]
H. Darabi and A. Abidi, "Noise in RF-CMOS mixers: a simple physical model," IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 15--25, Jan 2000.

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    cover image ACM Conferences
    SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system design
    September 2010
    228 pages
    ISBN:9781450301527
    DOI:10.1145/1854153
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 06 September 2010

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    Author Tags

    1. CMOS
    2. MMIC
    3. RFIC
    4. analog circuits
    5. broadband
    6. mixer

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