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Bit-level optimization for high-level synthesis and FPGA-based acceleration

Authors:

Jason CongAuthors Info & Claims

FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

Pages 59 - 68

https://doi.org/10.1145/1723112.1723124

Published: 21 February 2010 Publication History

Abstract

Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction.

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Cited By

Silitonga AKiyak YBecker J(2021)HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)10.1109/ASID52932.2021.9651483(122-128)Online publication date: 29-Oct-2021
https://doi.org/10.1109/ASID52932.2021.9651483
Baglij AMetelitsa EMikhailuts YIbragimov RSteinberg BSteinberg O(2020)On the Development of the Compiler from C to the Processor with FPGA AcceleratorFrontiers in Software Engineering Education10.1007/978-3-030-57663-9_25(386-400)Online publication date: 12-Aug-2020
https://doi.org/10.1007/978-3-030-57663-9_25
Siddiqui FAmiri SMinhas UDeng TWoods RRafferty KCrookes D(2019)FPGA-Based Processor Acceleration for Image Processing ApplicationsJournal of Imaging10.3390/jimaging50100165:1(16)Online publication date: 13-Jan-2019
https://doi.org/10.3390/jimaging5010016
Show More Cited By

Index Terms

Bit-level optimization for high-level synthesis and FPGA-based acceleration
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Information

Published In

cover image ACM Conferences

FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

February 2010

308 pages

ISBN:9781605589114

DOI:10.1145/1723112

General Chair:
Peter Cheung
Imperial College London, UK
,
Program Chair:
John Wawrzynek
UC Berkeley, USA

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 February 2010

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FPGA '10

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SIGDA

FPGA '10: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 21 - 23, 2010

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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FPGA '25

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The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

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Cited By

Silitonga AKiyak YBecker J(2021)HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)10.1109/ASID52932.2021.9651483(122-128)Online publication date: 29-Oct-2021
https://doi.org/10.1109/ASID52932.2021.9651483
Baglij AMetelitsa EMikhailuts YIbragimov RSteinberg BSteinberg O(2020)On the Development of the Compiler from C to the Processor with FPGA AcceleratorFrontiers in Software Engineering Education10.1007/978-3-030-57663-9_25(386-400)Online publication date: 12-Aug-2020
https://doi.org/10.1007/978-3-030-57663-9_25
Siddiqui FAmiri SMinhas UDeng TWoods RRafferty KCrookes D(2019)FPGA-Based Processor Acceleration for Image Processing ApplicationsJournal of Imaging10.3390/jimaging50100165:1(16)Online publication date: 13-Jan-2019
https://doi.org/10.3390/jimaging5010016
Azarbad MAlizadeh B(2016)Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/295387922:2(1-22)Online publication date: 26-Dec-2016
https://dl.acm.org/doi/10.1145/2953879
Zhao RTan MDai SZhang Z(2015)Area-efficient pipelining for FPGA-targeted high-level synthesisProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744801(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744801
Tan MDai SGupta UZhang ZConstantinides GChen D(2015)Mapping-Aware Constrained Scheduling for LUT-Based FPGAsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689063(190-199)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689063
Diaz IWilhelmsson LSofotasios PMiao YTan SEdfors OÖwall V(2015)A New Approach to Sign-Bit-Based Parameter Estimation in OFDM ReceiversCircuits, Systems, and Signal Processing10.1007/s00034-015-0025-534:11(3631-3660)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1007/s00034-015-0025-5
Ya. Steinberg BV. Dubrov DMikhailuts YRoshal ASteinberg R(2015)Automatic High-level Programs Mapping onto Programmable ArchitecturesProceedings of the 13th International Conference on Parallel Computing Technologies - Volume 925110.1007/978-3-319-21909-7_46(474-485)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1007/978-3-319-21909-7_46
Matai JKim JKastner R(2014)Energy efficient canonical huffman encoding2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2014.6868663(202-209)Online publication date: Jun-2014
https://doi.org/10.1109/ASAP.2014.6868663
Llopard ICohen AFabre CMartin JCharles HBernard CBrandner FAa T(2013)Code generation for an application-specific VLIW processor with clustered, addressable register filesProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443612(11-19)Online publication date: 24-Feb-2013
https://dl.acm.org/doi/10.1145/2443608.2443612
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