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Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Authors:

Srinivasan Murali,

Marco Domenico Santambrogio,

Donatella SciutoAuthors Info & Claims

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 325 - 334

https://doi.org/10.1145/1629435.1629480

Published: 11 October 2009 Publication History

Abstract

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation support for partial reconfigurability includes several key challenges. In particular, reconfiguration algorithms need to be developed to effectively exploit the available area and run-time reconfiguration support for instantiating at run-time the hardware components needed to execute multiple applications concurrently. These new algorithms must be able to achieve maximum application execution performance at a minimum reconfiguration overhead.

In this work, we propose a novel design flow that minimizes the amount of core reconfigurations needed to map multiple applications dynamically (i.e., using run-time reconfiguration) on FPGAs. This new mapping flow features a multi-stage design optimization algorithm that makes it possible to reduce the reconfiguration latency up to 43%, by taking into account the reconfiguration costs and SoC block reuse between the different applications that need to be executed dynamically on the FPGA. Moreover, we show that the proposed multi-stage optimization algorithm explores a large set of mapping trade-offs, by taking into account the traffic flows for each application, the run-time reconfiguration costs and the number of reconfigurable regions available on the FPGA.

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Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Tang QWang ZGuo BZhu LWei J(2020)Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/340370213:3(1-24)Online publication date: 21-Aug-2020
https://dl.acm.org/doi/10.1145/3403702
Vipin KFahmy S(2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3193827
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Index Terms

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Information & Contributors

Information

Published In

cover image ACM Conferences

CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

October 2009

498 pages

ISBN:9781605586281

DOI:10.1145/1629435

Program Chairs:
Wolfgang Rosenstiel
University of Tübingen, Germany
,
Kazutoshi Wakabayashi
NEC, Japan

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 October 2009

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ESWeek '09

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ESWeek '09: Fifth Embedded Systems Week

October 11 - 16, 2009

Grenoble, France

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Ding BHuang JWang JXu QChen SKang Y(2023)Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous ResourcesACM Transactions on Design Automation of Electronic Systems10.1145/362529528:6(1-26)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3625295
Tang QWang ZGuo BZhu LWei J(2020)Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/340370213:3(1-24)Online publication date: 21-Aug-2020
https://dl.acm.org/doi/10.1145/3403702
Vipin KFahmy S(2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3193827
Cai XHu WMa TMa R(2018)A hybrid scheduling algorithm for reconfigurable processor architecture2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA)10.1109/ICIEA.2018.8397812(745-749)Online publication date: May-2018
https://doi.org/10.1109/ICIEA.2018.8397812
Grudnitsky ABauer LHenkel JBetz VConstantinides G(2014)MORPProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554782(127-136)Online publication date: 26-Feb-2014
https://dl.acm.org/doi/10.1145/2554688.2554782
Lyons MWei GBrooks D(2013)Shrink-FitIEEE Computer Architecture Letters10.1109/L-CA.2012.712:1(17-20)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1109/L-CA.2012.7
Vipin KFahmy S(2013)Automated Partitioning for Partial Reconfiguration Design of Adaptive SystemsProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.119(172-181)Online publication date: 20-May-2013
https://dl.acm.org/doi/10.1109/IPDPSW.2013.119
Durelli GPilato CCazzaniga ASciuto DSantambrogio M(2012)Automatic run-time manager generation for reconfigurable MPSoC architectures7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2012.6322883(1-8)Online publication date: Jul-2012
https://doi.org/10.1109/ReCoSoC.2012.6322883
Beretta IRana VAtienza DSciuto D(2011)A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.213814030:8(1211-1224)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2138140
Beretta IRana VAtienza DSciuto D(2011)Island-Based Adaptable Embedded System DesignIEEE Embedded Systems Letters10.1109/LES.2011.21159913:2(53-57)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1109/LES.2011.2115991
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