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High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV

Published: 31 August 2009 Publication History

Abstract

This work presents a high throughput and low cost architecture for the Context Adaptive Variable Length Decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD in H.264/AVC since a large number of syntax elements are decoded based on look-up tables. To solve this problem, we propose an efficient decoding of syntax elements through the use of tree structures. Due to the difficulty to parallelize operations with variable length codes, we have proposed a few optimizations aiming to improve performance, and these optimizations are presented in this paper. The designed architecture was described in VHDL and synthesized to TSMC 0.18μm CMOS standard-cells technology. The obtained results show that this solution reached the necessary throughput to decode HDTV videos (1920x1080 pixels) in real-time (30fps).

References

[1]
Joint Video Team of ITU-T, and ISO/IEC JTC 1: Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 or ISO/IEC 14496-10 AVC). JVT Document, JVT-G050r1, 2003.
[2]
INTERNATIONAL TELECOMMUNICATION UNION. ITU-T Recommendation H.264 (03/05): Advanced Video Coding for Generic Audiovisual Services, 2005.
[3]
Richardson, I., H.264 and MPEG-4 Video Compression -- Video Coding for Next-Generation Multimedia. Chichester: John Wiley and Sons, 2003.
[4]
Lin, H., Lu, Y., Liu, B. and Yang, J., "A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder," Proc. IEEE Trans. On Multimedia, vol. 10, Jan. 2008, pp. 31--42.
[5]
Tsai, T. and Fang, D., "An Efficient CAVLD Algorithm for H.264 Decoder," Proc. ICCE, 2008.
[6]
Yu, G. and Chang, T., "A Zero-Skipping Multisymbol CAVLC Decoder for MPEG-4 AVC/H.264," Proc. ISCAS, 2006, pp. 21--24.
[7]
Alle, M., Biswas, J. and Nandy, S. K., "High Performance VLSI Architecture Design for H.264 CAVLC Decoder," Proc. ASAP, 2006, pp. 317--322.

Cited By

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  • (2019)High-Throughput Reconfigurable Variable Length Coding Decoder for MPEG-2 and AVC/H.264Journal of Signal Processing Systems10.1007/s11265-015-0979-382:1(27-40)Online publication date: 17-Jan-2019

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  1. High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV

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    cover image ACM Conferences
    SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
    August 2009
    325 pages
    ISBN:9781605587059
    DOI:10.1145/1601896
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 31 August 2009

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    Author Tags

    1. CAVLD
    2. H.264/AVC
    3. hardware architectures
    4. video compression

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    SBCCI '09 Paper Acceptance Rate 50 of 119 submissions, 42%;
    Overall Acceptance Rate 133 of 347 submissions, 38%

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    • (2019)High-Throughput Reconfigurable Variable Length Coding Decoder for MPEG-2 and AVC/H.264Journal of Signal Processing Systems10.1007/s11265-015-0979-382:1(27-40)Online publication date: 17-Jan-2019

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