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Quadratic Boolean programming for performance-driven system partitioning

Authors:

Minshine Shih,

Ernest S. KuhAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 761 - 765

https://doi.org/10.1145/157485.165121

Published: 01 July 1993 Publication History

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References

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Cited By

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Blutman KFatemi HKapoor AKahng ALi JPineda de Gyvez J(2017)Logic Design Partitioning for Stacked Power DomainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272958725:11(3045-3056)Online publication date: Nov-2017
https://doi.org/10.1109/TVLSI.2017.2729587
Blutman KFatemi HKahng AKapoor ALi Jde Gyvez J(2017)Floorplan and placement methodology for improved energy reduction in stacked power-domain design2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858363(444-449)Online publication date: Jan-2017
https://doi.org/10.1109/ASPDAC.2017.7858363
Cheng CChang YHu J(2011)Placement and beyond in honor of Ernest S. KuhProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960402(5-8)Online publication date: 27-Mar-2011
https://dl.acm.org/doi/10.1145/1960397.1960402
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Index Terms

Quadratic Boolean programming for performance-driven system partitioning
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Integrated circuits
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Computations on matrices

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Blutman KFatemi HKapoor AKahng ALi JPineda de Gyvez J(2017)Logic Design Partitioning for Stacked Power DomainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.272958725:11(3045-3056)Online publication date: Nov-2017
https://doi.org/10.1109/TVLSI.2017.2729587
Blutman KFatemi HKahng AKapoor ALi Jde Gyvez J(2017)Floorplan and placement methodology for improved energy reduction in stacked power-domain design2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858363(444-449)Online publication date: Jan-2017
https://doi.org/10.1109/ASPDAC.2017.7858363
Cheng CChang YHu J(2011)Placement and beyond in honor of Ernest S. KuhProceedings of the 2011 international symposium on Physical design10.1145/1960397.1960402(5-8)Online publication date: 27-Mar-2011
https://dl.acm.org/doi/10.1145/1960397.1960402
Stanisavljević MSchmid ALeblebici YStanisavljević MSchmid ALeblebici Y(2010)Design Methodology: Reliability Evaluation and OptimizationReliability of Nanoscale Circuits and Systems10.1007/978-1-4419-6217-1_8(121-166)Online publication date: 21-Sep-2010
https://doi.org/10.1007/978-1-4419-6217-1_8
Lung-Tien Liu (2006)Performance-Driven Partitioning Using a Replication Graph Approach32nd Design Automation Conference10.1109/DAC.1995.250091(206-210)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250091
Kim CShin H(2006)A performance-driven logic emulation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50614315:5(560-568)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.506143
Ababei CBazargan K(2003)Timing Minimization by Statistical Timing hMetis-based PartitioningProceedings of the 16th International Conference on VLSI Design10.5555/832285.835619Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835619
Ababei CBazargan K(2003)Timing minimization by statistical timing hMetis-based partitioning16th International Conference on VLSI Design, 2003. Proceedings.10.1109/ICVD.2003.1183115(58-63)Online publication date: 2003
https://doi.org/10.1109/ICVD.2003.1183115
Shihliang Ou Pedram M(1999)Timing-driven bipartitioning with replication using iterative quadratic programmingProceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)10.1109/ASPDAC.1999.759724(105-108 vol.1)Online publication date: 1999
https://doi.org/10.1109/ASPDAC.1999.759724
Behrens DHarbich KBarke ERutenbar ROtten R(1997)Hierarchical partitioningProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244861(470-477)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.5555/244522.244861
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