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Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments

Authors:

Tien-Chien Lee,

Niraj K. Jha,

Wayne H. WolfAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 292 - 297

https://doi.org/10.1145/157485.164897

Published: 01 July 1993 Publication History

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Cited By

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Masuda TNishimaki JHosokawa TFujiwara H(2015)A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller AugmentationProceedings of the 2015 IEEE 24th Asian Test Symposium (ATS)10.1109/ATS.2015.14(37-42)Online publication date: 22-Nov-2015
https://dl.acm.org/doi/10.1109/ATS.2015.14
Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Aminzadeh SSafari SZhou HMacii EYan ZMassoud Y(2007)Co-evolutionary high-level test synthesisProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228805(67-72)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228805
Show More Cited By

Index Terms

Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
  2. Hardware test
    1. Design for testability
    2. Test-pattern generation and fault simulation
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Masuda TNishimaki JHosokawa TFujiwara H(2015)A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller AugmentationProceedings of the 2015 IEEE 24th Asian Test Symposium (ATS)10.1109/ATS.2015.14(37-42)Online publication date: 22-Nov-2015
https://dl.acm.org/doi/10.1109/ATS.2015.14
Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Aminzadeh SSafari SZhou HMacii EYan ZMassoud Y(2007)Co-evolutionary high-level test synthesisProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228805(67-72)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228805
Boubezari SCerny EKaminska BNadeau-Dostie B(2006)Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BISTIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.78412418:9(1327-1340)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.784124
Potkonjak MSrivastava M(2006)Behavioral optimization using the manipulation of timing constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.72891517:10(936-947)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.728915
Ghosh IRaghunathan AJha N(2006)A design-for-testability technique for register-transfer level circuits using control/data flow extractionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.71210217:8(706-723)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.712102
Dey SGangaram VPotkonjak M(2006)A controller redesign technique to enhance testability of controller-data path circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126517:2(157-168)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.681265
Dey SPotkonjak M(2006)Nonscan design-for-testability techniques using RT-level design informationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66423016:12(1488-1506)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.664230
Ghosh IRaghunathan AJha N(2006)Design for hierarchical testability of RTL circuits obtained by behavioral synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.65856816:9(1001-1014)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.658568
Potkonjak MDey SRoy R(2006)Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40671514:9(1141-1154)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.406715
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