research-article

Secure processing using dynamic partial reconfiguration

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Gregory D. PetersonAuthors Info & Claims

CSIIRW '09: Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies

Article No.: 58, Pages 1 - 4

https://doi.org/10.1145/1558607.1558674

Published: 13 April 2009 Publication History

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Abstract

A popular research topic as of late has been dynamic partial FPGA (Field Programmable Gate Array) reconfiguration. This concept allows on-the-fly reconfiguration of digital systems where only parts of the circuit change, providing application acceleration and allowing static modules to continue processing unaffected by the dynamic elements. Design characteristics which benefit from this progressive approach include increased system flexibility, increased performance, and a reduction in circuit complexity. One characteristic receiving limited focus thus far has been the increased security that could result from these changing circuits. This benefit is innate to the design and makes reverse engineering of the system a much more ambitious task. In an effort to further enhance this passive security feature, a new partial reconfiguration technique has been proposed that changes connectivity between generic modules. This extended abstract introduces the method, model, and design flow for this dynamic partial FPGA reconfiguration technique and addresses the security implications of such a design.

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Cited By

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Saeed AAhmadinia AJust M(2018)Hardware-Assisted Secure Communication in Embedded and Multi-Core Computing SystemsComputers10.3390/computers70200317:2(31)Online publication date: 15-May-2018
https://doi.org/10.3390/computers7020031
Straka MKastil JKotasek Z(2010)Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems10.1109/DDECS.2010.5491793(173-176)Online publication date: Apr-2010
https://doi.org/10.1109/DDECS.2010.5491793

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CSIIRW '09: Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies

April 2009

952 pages

ISBN:9781605585185

DOI:10.1145/1558607

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 13 April 2009

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CSIIRW '09

CSIIRW '09: Fifth Cyber Security and Information Intelligence Research Workshop

April 13 - 15, 2009

Tennessee, Oak Ridge, USA

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Saeed AAhmadinia AJust M(2018)Hardware-Assisted Secure Communication in Embedded and Multi-Core Computing SystemsComputers10.3390/computers70200317:2(31)Online publication date: 15-May-2018
https://doi.org/10.3390/computers7020031
Straka MKastil JKotasek Z(2010)Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems10.1109/DDECS.2010.5491793(173-176)Online publication date: Apr-2010
https://doi.org/10.1109/DDECS.2010.5491793

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FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications

SeReCon: a secure reconfiguration controller for self-reconfigurable systems

High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing