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Stretching transactional memory

Published: 15 June 2009 Publication History

Abstract

Transactional memory (TM) is an appealing abstraction for programming multi-core systems. Potential target applications for TM, such as business software and video games, are likely to involve complex data structures and large transactions, requiring specific software solutions (STM). So far, however, STMs have been mainly evaluated and optimized for smaller scale benchmarks.
We revisit the main STM design choices from the perspective of complex workloads and propose a new STM, which we call SwissTM. In short, SwissTM is lock- and word-based and uses (1) optimistic (commit-time) conflict detection for read/write conflicts and pessimistic (encounter-time) conflict detection for write/write conflicts, as well as (2) a new two-phase contention manager that ensures the progress of long transactions while inducing no overhead on short ones. SwissTM outperforms state-of-the-art STM implementations, namely RSTM, TL2, and TinySTM, in our experiments on STMBench7, STAMP, Lee-TM and red-black tree benchmarks.
Beyond SwissTM, we present the most complete evaluation to date of the individual impact of various STM design choices on the ability to support the mixed workloads of large applications.

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Cited By

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  • (2023)CSMV: A highly scalable multi-versioned software transactional memory for GPUsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.04.002180(104701)Online publication date: Oct-2023
  • (2022)CSMV: A Highly Scalable Multi-Versioned Software Transactional Memory for GPUs2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS53621.2022.00057(526-536)Online publication date: May-2022
  • (2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
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Published In

cover image ACM Conferences
PLDI '09: Proceedings of the 30th ACM SIGPLAN Conference on Programming Language Design and Implementation
June 2009
492 pages
ISBN:9781605583921
DOI:10.1145/1542476
  • cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 44, Issue 6
    PLDI '09
    June 2009
    478 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/1543135
    Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 15 June 2009

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  1. benchmarks
  2. software transactional memories

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Cited By

View all
  • (2023)CSMV: A highly scalable multi-versioned software transactional memory for GPUsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.04.002180(104701)Online publication date: Oct-2023
  • (2022)CSMV: A Highly Scalable Multi-Versioned Software Transactional Memory for GPUs2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS53621.2022.00057(526-536)Online publication date: May-2022
  • (2021)Adaptive Versioning in Transactional Memory SystemsAlgorithms10.3390/a1406017114:6(171)Online publication date: 31-May-2021
  • (2021)An extension for Transactional Memory in OpenMPProceedings of the 25th Brazilian Symposium on Programming Languages10.1145/3475061.3475089(58-65)Online publication date: 27-Sep-2021
  • (2020)Opportunities for optimism in contended main-memory multicore transactionsProceedings of the VLDB Endowment10.14778/3377369.337737313:5(629-642)Online publication date: 19-Feb-2020
  • (2020)Improving Transactional Code Generation via Variable Annotation and Barrier Elision2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00107(1008-1017)Online publication date: May-2020
  • (2019)Centralized Core-granular Scheduling for Serverless FunctionsProceedings of the ACM Symposium on Cloud Computing10.1145/3357223.3362709(158-164)Online publication date: 20-Nov-2019
  • (2019)MV-RLUProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304040(779-792)Online publication date: 4-Apr-2019
  • (2018)SundialProceedings of the VLDB Endowment10.14778/3231751.323176311:10(1289-1302)Online publication date: 1-Jun-2018
  • (2018)NemoProceedings of the 47th International Conference on Parallel Processing10.1145/3225058.3225123(1-10)Online publication date: 13-Aug-2018
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