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The expandable split window paradigm for exploiting fine-grain parallelsim

Authors:

Manoj Franklin,

Gurindar S. SohiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 20, Issue 2

Pages 58 - 67

https://doi.org/10.1145/146628.139703

Published: 01 April 1992 Publication History

Abstract

We propose a new processing paradigm, called the Expandable Split Window (ESW) paradigm, for exploiting fine-grain parallelism. This paradigm considers a window of instructions (possibly having dependencies) as a single unit, and exploits fine-grain parallelism by overlapping the execution of multiple windows. The basic idea is to connect multiple sequential processors, in a decoupled and decentralized manner, to achieve overall multiple issue. This processing paradigm shares a number of properties of the restricted dataflow machines, but was derived from the sequential von Neumann architecture. We also present an implementation of the Expandable Split Window execution model, and preliminary performance results.

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Le HGuthrie GWilliams DMichael MFrey BStarke WMay COdaira RNakaike T(2015)Transactional memory support in the IBM POWER8 processorIBM Journal of Research and Development10.1147/JRD.2014.238019959:1(8:1-8:14)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1147/JRD.2014.2380199
Sanchez JMarcuello PGonzález A(2010)Multithreading and SpeculationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch13(333-353)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch13
Pei SWu BDu MChen GMarzulo LFranca F(2009)SpMT WaveCacheProceedings of the 2009 WRI World Congress on Computer Science and Information Engineering - Volume 0310.1109/CSIE.2009.35(530-535)Online publication date: 31-Mar-2009
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Index Terms

The expandable split window paradigm for exploiting fine-grain parallelsim
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 20, Issue 2

Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

May 1992

429 pages

ISSN:0163-5964

DOI:10.1145/146628

Editor:
Allan Gotlieb
New York Univ., New York, NY

Issue’s Table of Contents

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture
May 1992
439 pages
ISBN:0897915097
DOI:10.1145/139669
Chairman:
Allan Gottlieb
New York Unvi., New York, NY

Copyright © 1992 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

Published in SIGARCH Volume 20, Issue 2

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Cited By

Le HGuthrie GWilliams DMichael MFrey BStarke WMay COdaira RNakaike T(2015)Transactional memory support in the IBM POWER8 processorIBM Journal of Research and Development10.1147/JRD.2014.238019959:1(8:1-8:14)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1147/JRD.2014.2380199
Sanchez JMarcuello PGonzález A(2010)Multithreading and SpeculationSpeculative Execution in High Performance Computer Architectures10.1201/9781420035155.ch13(333-353)Online publication date: 14-Jan-2010
https://doi.org/10.1201/9781420035155.ch13
Pei SWu BDu MChen GMarzulo LFranca F(2009)SpMT WaveCacheProceedings of the 2009 WRI World Congress on Computer Science and Information Engineering - Volume 0310.1109/CSIE.2009.35(530-535)Online publication date: 31-Mar-2009
https://dl.acm.org/doi/10.1109/CSIE.2009.35
Sohi GVijaykumar T(2009)Speculatively Multithreaded ArchitecturesMulticore Processors and Systems10.1007/978-1-4419-0263-4_4(111-143)Online publication date: 3-Aug-2009
https://doi.org/10.1007/978-1-4419-0263-4_4
Wu PKejariwal ACaşcaval C(2008)Compiler-Driven Dependence Profiling to Guide Program ParallelizationLanguages and Compilers for Parallel Computing10.1007/978-3-540-89740-8_16(232-248)Online publication date: 28-Nov-2008
https://dl.acm.org/doi/10.1007/978-3-540-89740-8_16
Zhang AHelal S(2007)SuperCacheProceedings of the International Conference on Information Technology10.1109/ITNG.2007.189(908-914)Online publication date: 2-Apr-2007
https://dl.acm.org/doi/10.1109/ITNG.2007.189
Ramirez MCristal AValero MVeidenbaum AVilla L(2005)A New Pointer-based Instruction Queue Design and Its Power-Performance EvaluationProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.12(647-653)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.12
Zyuban VKogge P(2001)Inherently Lower-Power High-Performance Superscalar ArchitecturesIEEE Transactions on Computers10.1109/12.91081650:3(268-285)Online publication date: 1-Mar-2001
https://dl.acm.org/doi/10.1109/12.910816
Daglis AUstiugov DNovaković SBugnion EFalsafi BGrot BHsu WYang CLipasti MLee H(2016)SABResThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195646(1-13)Online publication date: 15-Oct-2016
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