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research-article

Cycle-approximate retargetable performance estimation at the transaction level

Authors:

Yonghyun Hwang,

Daniel GajskiAuthors Info & Claims

DATE '08: Proceedings of the conference on Design, automation and test in Europe

Pages 3 - 8

https://doi.org/10.1145/1403375.1403380

Published: 10 March 2008 Publication History

Abstract

This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multi-core designs. The inputs are application C processes and their mapping to processing units in the platform. The processing unit model consists of pipelined datapath, memory hierarchy and branch delay model. Using the processing unit model, the basic blocks in the C processes are analyzed and annotated with estimated delays. This is followed by a code generation phase where delay-annotated C code is generated and linked with a SystemC wrapper consisting of inter-process communication channels. The generated TLM is compiled and executed natively on the host machine. Our key contribution is that the estimation technique is close to cycle-accurate, it can be applied to any multi-core platform and it produces high-speed native compiled TLMs. For experiments, timed TLMs for industrial scale designs such as MP3 decoder were automatically generated for 4 heterogeneous multi-processor platforms with up to 5 PEs under 1 minute. Each TLM simulated under 1 second, compared to 3--4 hrs of instruction set simulation (ISS) and 15--18 hrs of RTL simulation. Comparison to on-board measurement showed only 8% error on average in estimated number of cycles.

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Cited By

Wu HGuo DTsay R(2020)A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Inter-Component InteractionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977064(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.2977064
El-Sayed AEl-Farag AHanafy Y(2019)Data Layout Organization effect on Communication in Parallel Programs2019 29th International Conference on Computer Theory and Applications (ICCTA)10.1109/ICCTA48790.2019.9478826(79-83)Online publication date: 29-Oct-2019
https://doi.org/10.1109/ICCTA48790.2019.9478826
Roloff SHannig FTeich JRoloff SHannig FTeich J(2019)InvadeSIM-A Simulation Framework for Invasive Parallel Programs and ArchitecturesModeling and Simulation of Invasive Applications and Architectures10.1007/978-981-13-8387-8_3(41-76)Online publication date: 31-May-2019
https://doi.org/10.1007/978-981-13-8387-8_3
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Index Terms

Cycle-approximate retargetable performance estimation at the transaction level
1. Hardware
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures

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cover image ACM Conferences

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

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DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Wu HGuo DTsay R(2020)A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Inter-Component InteractionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977064(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.2977064
El-Sayed AEl-Farag AHanafy Y(2019)Data Layout Organization effect on Communication in Parallel Programs2019 29th International Conference on Computer Theory and Applications (ICCTA)10.1109/ICCTA48790.2019.9478826(79-83)Online publication date: 29-Oct-2019
https://doi.org/10.1109/ICCTA48790.2019.9478826
Roloff SHannig FTeich JRoloff SHannig FTeich J(2019)InvadeSIM-A Simulation Framework for Invasive Parallel Programs and ArchitecturesModeling and Simulation of Invasive Applications and Architectures10.1007/978-981-13-8387-8_3(41-76)Online publication date: 31-May-2019
https://doi.org/10.1007/978-981-13-8387-8_3
Wijesundera DPrakash ASrikanthan TIhalage A(2018)Framework for Rapid Performance Estimation of Embedded Soft Core ProcessorsACM Transactions on Reconfigurable Technology and Systems10.1145/319580111:2(1-21)Online publication date: 26-Jul-2018
https://dl.acm.org/doi/10.1145/3195801
Leupers RAguilar MCastrillon JSheng W(2018)Software Compilation Techniques for Heterogeneous Embedded Multi-Core SystemsHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_28(1021-1062)Online publication date: 14-Oct-2018
https://doi.org/10.1007/978-3-319-91734-4_28
Zhao ZGerstlauer AJohn L(2017)Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257888236:2(299-312)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2578882
Saboori EAbdi S(2016)Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototypingProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2968470(1-10)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1145/2968456.2968470
Ittershagen PHartmann PGrüttner KNebel W(2015)A workload extraction framework for software performance model generationProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693436(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693436
Eusse JWilliams CLeupers R(2015)CoExACM Transactions on Reconfigurable Technology and Systems10.1145/26295638:3(1-16)Online publication date: 4-May-2015
https://dl.acm.org/doi/10.1145/2629563
Chen SChen CTsay RFettweis GNebel W(2014)An activity-sensitive contention delay model for highly efficient deterministic full-system simulationsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616868(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616868
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